340 lines
10 KiB
C
340 lines
10 KiB
C
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/* Copyright (C) 2007-2008 Jean-Marc Valin
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* Copyright (C) 2008 Thorvald Natvig
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* Copyright (C) 2011 Texas Instruments
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* author Jyri Sarha
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*/
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/**
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@file resample_neon.h
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@brief Resampler functions (NEON version)
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*/
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/*
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of the Xiph.org Foundation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifdef FIXED_POINT
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#if defined(__aarch64__)
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static inline int32_t saturate_32bit_to_16bit(int32_t a) {
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int32_t ret;
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asm ("fmov s0, %w[a]\n"
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"sqxtn h0, s0\n"
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"sxtl v0.4s, v0.4h\n"
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"fmov %w[ret], s0\n"
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: [ret] "=r" (ret)
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: [a] "r" (a)
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: "v0" );
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return ret;
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}
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#elif defined(__thumb2__)
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static inline int32_t saturate_32bit_to_16bit(int32_t a) {
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int32_t ret;
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asm ("ssat %[ret], #16, %[a]"
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: [ret] "=r" (ret)
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: [a] "r" (a)
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: );
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return ret;
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}
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#else
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static inline int32_t saturate_32bit_to_16bit(int32_t a) {
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int32_t ret;
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asm ("vmov.s32 d0[0], %[a]\n"
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"vqmovn.s32 d0, q0\n"
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"vmov.s16 %[ret], d0[0]\n"
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: [ret] "=r" (ret)
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: [a] "r" (a)
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: "q0");
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return ret;
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}
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#endif
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#undef WORD2INT
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#define WORD2INT(x) (saturate_32bit_to_16bit(x))
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#define OVERRIDE_INNER_PRODUCT_SINGLE
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/* Only works when len % 4 == 0 and len >= 4 */
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#if defined(__aarch64__)
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static inline int32_t inner_product_single(const int16_t *a, const int16_t *b, unsigned int len)
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{
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int32_t ret;
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uint32_t remainder = len % 16;
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len = len - remainder;
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asm volatile (" cmp %w[len], #0\n"
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" b.ne 1f\n"
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" ld1 {v16.4h}, [%[b]], #8\n"
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" ld1 {v20.4h}, [%[a]], #8\n"
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" subs %w[remainder], %w[remainder], #4\n"
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" smull v0.4s, v16.4h, v20.4h\n"
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" b.ne 4f\n"
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" b 5f\n"
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"1:"
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" ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [%[b]], #32\n"
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" ld1 {v20.4h, v21.4h, v22.4h, v23.4h}, [%[a]], #32\n"
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" subs %w[len], %w[len], #16\n"
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" smull v0.4s, v16.4h, v20.4h\n"
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" smlal v0.4s, v17.4h, v21.4h\n"
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" smlal v0.4s, v18.4h, v22.4h\n"
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" smlal v0.4s, v19.4h, v23.4h\n"
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" b.eq 3f\n"
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"2:"
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" ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [%[b]], #32\n"
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" ld1 {v20.4h, v21.4h, v22.4h, v23.4h}, [%[a]], #32\n"
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" subs %w[len], %w[len], #16\n"
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" smlal v0.4s, v16.4h, v20.4h\n"
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" smlal v0.4s, v17.4h, v21.4h\n"
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" smlal v0.4s, v18.4h, v22.4h\n"
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" smlal v0.4s, v19.4h, v23.4h\n"
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" b.ne 2b\n"
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"3:"
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" cmp %w[remainder], #0\n"
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" b.eq 5f\n"
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"4:"
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" ld1 {v18.4h}, [%[b]], #8\n"
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" ld1 {v22.4h}, [%[a]], #8\n"
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" subs %w[remainder], %w[remainder], #4\n"
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" smlal v0.4s, v18.4h, v22.4h\n"
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" b.ne 4b\n"
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"5:"
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" saddlv d0, v0.4s\n"
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" sqxtn s0, d0\n"
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" sqrshrn h0, s0, #15\n"
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" sxtl v0.4s, v0.4h\n"
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" fmov %w[ret], s0\n"
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: [ret] "=r" (ret), [a] "+r" (a), [b] "+r" (b),
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[len] "+r" (len), [remainder] "+r" (remainder)
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:
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: "cc", "v0",
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"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23");
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return ret;
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}
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#else
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static inline int32_t inner_product_single(const int16_t *a, const int16_t *b, unsigned int len)
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{
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int32_t ret;
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uint32_t remainder = len % 16;
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len = len - remainder;
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asm volatile (" cmp %[len], #0\n"
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" bne 1f\n"
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" vld1.16 {d16}, [%[b]]!\n"
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" vld1.16 {d20}, [%[a]]!\n"
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" subs %[remainder], %[remainder], #4\n"
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" vmull.s16 q0, d16, d20\n"
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" beq 5f\n"
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" b 4f\n"
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"1:"
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" vld1.16 {d16, d17, d18, d19}, [%[b]]!\n"
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" vld1.16 {d20, d21, d22, d23}, [%[a]]!\n"
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" subs %[len], %[len], #16\n"
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" vmull.s16 q0, d16, d20\n"
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" vmlal.s16 q0, d17, d21\n"
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" vmlal.s16 q0, d18, d22\n"
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" vmlal.s16 q0, d19, d23\n"
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" beq 3f\n"
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"2:"
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" vld1.16 {d16, d17, d18, d19}, [%[b]]!\n"
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" vld1.16 {d20, d21, d22, d23}, [%[a]]!\n"
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" subs %[len], %[len], #16\n"
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" vmlal.s16 q0, d16, d20\n"
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" vmlal.s16 q0, d17, d21\n"
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" vmlal.s16 q0, d18, d22\n"
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" vmlal.s16 q0, d19, d23\n"
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" bne 2b\n"
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"3:"
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" cmp %[remainder], #0\n"
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" beq 5f\n"
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"4:"
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" vld1.16 {d16}, [%[b]]!\n"
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" vld1.16 {d20}, [%[a]]!\n"
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" subs %[remainder], %[remainder], #4\n"
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" vmlal.s16 q0, d16, d20\n"
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" bne 4b\n"
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"5:"
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" vaddl.s32 q0, d0, d1\n"
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" vadd.s64 d0, d0, d1\n"
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" vqmovn.s64 d0, q0\n"
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" vqrshrn.s32 d0, q0, #15\n"
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" vmov.s16 %[ret], d0[0]\n"
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: [ret] "=r" (ret), [a] "+r" (a), [b] "+r" (b),
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[len] "+r" (len), [remainder] "+r" (remainder)
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:
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: "cc", "q0",
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"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23");
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return ret;
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}
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#endif // !defined(__aarch64__)
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#elif defined(FLOATING_POINT)
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#if defined(__aarch64__)
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static inline int32_t saturate_float_to_16bit(float a) {
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int32_t ret;
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asm ("fcvtas s1, %s[a]\n"
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"sqxtn h1, s1\n"
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"sxtl v1.4s, v1.4h\n"
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"fmov %w[ret], s1\n"
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: [ret] "=r" (ret)
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: [a] "w" (a)
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: "v1");
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return ret;
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}
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#else
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static inline int32_t saturate_float_to_16bit(float a) {
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int32_t ret;
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asm ("vmov.f32 d0[0], %[a]\n"
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"vcvt.s32.f32 d0, d0, #15\n"
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"vqrshrn.s32 d0, q0, #15\n"
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"vmov.s16 %[ret], d0[0]\n"
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: [ret] "=r" (ret)
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: [a] "r" (a)
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: "q0");
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return ret;
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}
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#endif
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#undef WORD2INT
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#define WORD2INT(x) (saturate_float_to_16bit(x))
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#define OVERRIDE_INNER_PRODUCT_SINGLE
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/* Only works when len % 4 == 0 and len >= 4 */
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#if defined(__aarch64__)
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static inline float inner_product_single(const float *a, const float *b, unsigned int len)
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{
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float ret;
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uint32_t remainder = len % 16;
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len = len - remainder;
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asm volatile (" cmp %w[len], #0\n"
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" b.ne 1f\n"
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" ld1 {v16.4s}, [%[b]], #16\n"
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" ld1 {v20.4s}, [%[a]], #16\n"
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" subs %w[remainder], %w[remainder], #4\n"
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" fmul v1.4s, v16.4s, v20.4s\n"
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" b.ne 4f\n"
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" b 5f\n"
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"1:"
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" ld1 {v16.4s, v17.4s, v18.4s, v19.4s}, [%[b]], #64\n"
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" ld1 {v20.4s, v21.4s, v22.4s, v23.4s}, [%[a]], #64\n"
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" subs %w[len], %w[len], #16\n"
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" fmul v1.4s, v16.4s, v20.4s\n"
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" fmul v2.4s, v17.4s, v21.4s\n"
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" fmul v3.4s, v18.4s, v22.4s\n"
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" fmul v4.4s, v19.4s, v23.4s\n"
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" b.eq 3f\n"
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"2:"
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" ld1 {v16.4s, v17.4s, v18.4s, v19.4s}, [%[b]], #64\n"
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" ld1 {v20.4s, v21.4s, v22.4s, v23.4s}, [%[a]], #64\n"
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" subs %w[len], %w[len], #16\n"
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" fmla v1.4s, v16.4s, v20.4s\n"
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" fmla v2.4s, v17.4s, v21.4s\n"
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" fmla v3.4s, v18.4s, v22.4s\n"
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" fmla v4.4s, v19.4s, v23.4s\n"
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" b.ne 2b\n"
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"3:"
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" fadd v16.4s, v1.4s, v2.4s\n"
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" fadd v17.4s, v3.4s, v4.4s\n"
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" cmp %w[remainder], #0\n"
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" fadd v1.4s, v16.4s, v17.4s\n"
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" b.eq 5f\n"
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"4:"
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" ld1 {v18.4s}, [%[b]], #16\n"
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" ld1 {v22.4s}, [%[a]], #16\n"
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" subs %w[remainder], %w[remainder], #4\n"
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" fmla v1.4s, v18.4s, v22.4s\n"
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" b.ne 4b\n"
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"5:"
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" faddp v1.4s, v1.4s, v1.4s\n"
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" faddp %[ret].4s, v1.4s, v1.4s\n"
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: [ret] "=w" (ret), [a] "+r" (a), [b] "+r" (b),
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[len] "+r" (len), [remainder] "+r" (remainder)
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:
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: "cc", "v1", "v2", "v3", "v4",
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"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23");
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return ret;
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}
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#else
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static inline float inner_product_single(const float *a, const float *b, unsigned int len)
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{
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float ret;
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uint32_t remainder = len % 16;
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len = len - remainder;
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asm volatile (" cmp %[len], #0\n"
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" bne 1f\n"
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" vld1.32 {q4}, [%[b]]!\n"
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" vld1.32 {q8}, [%[a]]!\n"
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" subs %[remainder], %[remainder], #4\n"
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" vmul.f32 q0, q4, q8\n"
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" bne 4f\n"
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" b 5f\n"
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"1:"
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" vld1.32 {q4, q5}, [%[b]]!\n"
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" vld1.32 {q8, q9}, [%[a]]!\n"
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" vld1.32 {q6, q7}, [%[b]]!\n"
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" vld1.32 {q10, q11}, [%[a]]!\n"
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" subs %[len], %[len], #16\n"
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" vmul.f32 q0, q4, q8\n"
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" vmul.f32 q1, q5, q9\n"
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" vmul.f32 q2, q6, q10\n"
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" vmul.f32 q3, q7, q11\n"
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" beq 3f\n"
|
||
|
|
"2:"
|
||
|
|
" vld1.32 {q4, q5}, [%[b]]!\n"
|
||
|
|
" vld1.32 {q8, q9}, [%[a]]!\n"
|
||
|
|
" vld1.32 {q6, q7}, [%[b]]!\n"
|
||
|
|
" vld1.32 {q10, q11}, [%[a]]!\n"
|
||
|
|
" subs %[len], %[len], #16\n"
|
||
|
|
" vmla.f32 q0, q4, q8\n"
|
||
|
|
" vmla.f32 q1, q5, q9\n"
|
||
|
|
" vmla.f32 q2, q6, q10\n"
|
||
|
|
" vmla.f32 q3, q7, q11\n"
|
||
|
|
" bne 2b\n"
|
||
|
|
"3:"
|
||
|
|
" vadd.f32 q4, q0, q1\n"
|
||
|
|
" vadd.f32 q5, q2, q3\n"
|
||
|
|
" cmp %[remainder], #0\n"
|
||
|
|
" vadd.f32 q0, q4, q5\n"
|
||
|
|
" beq 5f\n"
|
||
|
|
"4:"
|
||
|
|
" vld1.32 {q6}, [%[b]]!\n"
|
||
|
|
" vld1.32 {q10}, [%[a]]!\n"
|
||
|
|
" subs %[remainder], %[remainder], #4\n"
|
||
|
|
" vmla.f32 q0, q6, q10\n"
|
||
|
|
" bne 4b\n"
|
||
|
|
"5:"
|
||
|
|
" vadd.f32 d0, d0, d1\n"
|
||
|
|
" vpadd.f32 d0, d0, d0\n"
|
||
|
|
" vmov.f32 %[ret], d0[0]\n"
|
||
|
|
: [ret] "=r" (ret), [a] "+r" (a), [b] "+r" (b),
|
||
|
|
[len] "+l" (len), [remainder] "+l" (remainder)
|
||
|
|
:
|
||
|
|
: "cc", "q0", "q1", "q2", "q3",
|
||
|
|
"q4", "q5", "q6", "q7", "q8", "q9", "q10", "q11");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
#endif // defined(__aarch64__)
|
||
|
|
#endif
|