Got the VCO output inverted (and the signal as well), so now the output and the input are actually in phase.
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parent
20a2cdc73c
commit
88068ec517
1 changed files with 4 additions and 4 deletions
8
csdr.c
8
csdr.c
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@ -1987,10 +1987,10 @@ int main(int argc, char *argv[])
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FEOF_CHECK;
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FREAD_C;
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//pll_cc(&pll, (complexf*)input_buffer, NULL, (complexf*)output_buffer, the_bufsize);
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//fprintf(stderr, "| i");
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//pll_cc(&pll, (complexf*)input_buffer, output_buffer, NULL, the_bufsize);
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pll_cc(&pll, (complexf*)input_buffer, NULL, (complexf*)output_buffer, the_bufsize);
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fwrite(output_buffer, sizeof(complexf), the_bufsize, stdout);
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// fprintf(stderr, "| i");
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pll_cc(&pll, (complexf*)input_buffer, output_buffer, NULL, the_bufsize);
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//pll_cc(&pll, (complexf*)input_buffer, NULL, (complexf*)output_buffer, the_bufsize);
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fwrite(output_buffer, sizeof(float), the_bufsize, stdout);
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//fprintf(stderr, "| o");
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TRY_YIELD;
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}
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