Extend fundamental frequency up to 1GHZ using PDIV PLL. Rewrite divider choice
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F5OEO
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6148190afa
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1dac6e6948
1 changed files with 89 additions and 68 deletions
157
src/gpio.cpp
157
src/gpio.cpp
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@ -169,7 +169,7 @@ int clkgpio::SetFrequency(double Frequency)
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if ((FreqDivider > 4096) || (FreqDivider < 2))
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fprintf(stderr, "Frequency out of range\n");
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printf("DIV/FRAC %u/%u \n", FreqDivider, FreqFractionnal);
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SetClkDivFrac(FreqDivider, FreqFractionnal);
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}
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@ -197,67 +197,66 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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// Choose an integer divider for GPCLK0
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//
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// There may be improvements possible to this algorithm.
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double xtal_freq_recip = 1.0 / 19.2e6; // todo PPM correction
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// Constants taken https://github.com/raspberrypi/linux/blob/ffd7bf4085b09447e5db96edd74e524f118ca3fe/drivers/clk/bcm/clk-bcm2835.c#L1763
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#define MIN_PLL_RATE 400e6
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#define MIN_PLL_RATE_USE_PDIV 1700e6
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#define MAX_PLL_RATE 3e9
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#define XTAL_RATE 19.2e6
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double xtal_freq_recip = 1.0 / XTAL_RATE; // todo PPM correction
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int best_divider = 0;
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int solution_count = 0;
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//printf("carrier:%3.2f ",carrier_freq/1e6);
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int divider, min_int_multiplier, max_int_multiplier, fom, int_multiplier, best_fom = 0;
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double frac_multiplier;
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int divider=0, min_int_multiplier, max_int_multiplier, fom, int_multiplier, best_fom = 0;
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best_divider = 0;
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for (divider = 2; divider < 4096; divider++)//1 is allowed only for MASH=0
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bool cross_boundary=false;
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if(Frequency<MIN_PLL_RATE/4095)
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{
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if (Frequency * divider < 600e6)
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continue; // widest accepted frequency range
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if (Frequency * divider > 1700e6) // By Experiment on Rpi3B
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break;
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max_int_multiplier = ((int)((double)(Frequency + Bandwidth) * divider * xtal_freq_recip));
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min_int_multiplier = ((int)((double)(Frequency - Bandwidth) * divider * xtal_freq_recip));
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if (min_int_multiplier != max_int_multiplier)
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fprintf(stderr, "Frequency too low !!!!!!\n");
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return -1;
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}
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if(Frequency*2>MAX_PLL_RATE)
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{
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fprintf(stderr, "Frequency too high !!!!!!\n");
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return -1;
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}
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if(Frequency*2>MIN_PLL_RATE_USE_PDIV)
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best_divider=1; // We will use PREDIV 2 for PLL
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else
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{
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for (divider = 4095; divider > 1; divider--)//1 is allowed only for MASH=0
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{
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//fprintf(stderr,"Warning : cross boundary frequency\n");
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continue; // don't cross integer boundary
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}
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// continue; // don't cross integer boundary
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if (Frequency * divider < MIN_PLL_RATE)
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continue; // widest accepted frequency range
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if (Frequency * divider > MIN_PLL_RATE_USE_PDIV) // By Experiment on Rpi3B
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{
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continue;
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}
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max_int_multiplier = ((int)((double)(Frequency + Bandwidth) * divider * xtal_freq_recip));
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min_int_multiplier = ((int)((double)(Frequency - Bandwidth) * divider * xtal_freq_recip));
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if (min_int_multiplier != max_int_multiplier)
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{
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//fprintf(stderr,"Warning : cross boundary frequency\n");
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best_divider=divider;
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cross_boundary=true;
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continue; // don't cross integer boundary
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}
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else
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{
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cross_boundary=false;
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best_divider=divider;
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break;
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}
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solution_count++; // if we make it here the solution is acceptable,
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fom = 0; // but we want a good solution
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if (Frequency * divider > 900e6)
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fom++; // prefer freqs closer to 1000
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if (Frequency * divider < 1100e6)
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fom++;
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if (Frequency * divider > 800e6)
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fom++; // accepted frequency range
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if (Frequency * divider < 1200e6)
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fom++;
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frac_multiplier = ((double)(Frequency)*divider * xtal_freq_recip);
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int_multiplier = (int)frac_multiplier;
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frac_multiplier = frac_multiplier - int_multiplier;
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//if ((int_multiplier % 2) == 0)
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// fom++;
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//if (((frac_multiplier > 0.7) && (frac_multiplier < 1.0))||((frac_multiplier > 0.0) && (frac_multiplier < 0.3)))
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if (((frac_multiplier > 0.2) && (frac_multiplier < 0.3))||((frac_multiplier > 0.7) && (frac_multiplier < 0.8)))
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//if (((frac_multiplier > 0.4) && (frac_multiplier < 0.6)))
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fom += 2; // prefer mulipliers away from integer boundaries
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//if( divider%2 == 1 ) fom+=2; // prefer odd dividers
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// Even and odd dividers could have different harmonic content,
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// but the latest measurements have shown no significant difference.
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//printf("Try multiplier:%f divider:%d VCO: %4.1fMHz Spurious %f\n",Frequency*divider*xtal_freq_recip,divider,(double)Frequency*divider/1e6,frac_multiplier*19.2e6/(double)divider);
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if (fom > best_fom)
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{
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best_fom = fom;
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best_divider = divider;
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}
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}
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if (solution_count > 0)
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if (best_divider!=0)
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{
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PllFixDivider = best_divider;
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fprintf(stderr, " multiplier:%f divider:%d VCO: %4.1fMHz Spurious %f \n", Frequency * best_divider * xtal_freq_recip, best_divider, (double)Frequency * best_divider / 1e6,frac_multiplier*xtal_freq_recip/(double)divider);
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if(cross_boundary) fprintf(stderr,"Warning : cross boundary frequency\n");
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fprintf(stderr, "Found solution : divider:%d VCO: %4.1fMHz\n", best_divider,Frequency * best_divider * xtal_freq_recip);
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return 0;
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}
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else
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@ -308,9 +307,44 @@ int clkgpio::SetCenterFrequency(uint64_t Frequency, int Bandwidth)
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fprintf(stderr, "Master PLLC Locked\n");
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else
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fprintf(stderr, "Warning ! Master PLLC NOT Locked !!!!\n");
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SetClkDivFrac(PllFixDivider, 0x0); // NO MASH !!!!
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usleep(100);
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if(PllFixDivider==1)
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{
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//We will use PDIV by 2, means like we have a 2 times more
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SetClkDivFrac(2, 0x0); // NO MASH !!!!
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}
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else
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{
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SetClkDivFrac(PllFixDivider, 0x0); // NO MASH !!!!
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}
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// Apply PREDIV for PLL or not
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uint32_t ana[4];
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for (int i = 3; i >= 0; i--)
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{
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ana[i] = gpioreg[(A2W_PLLC_ANA0 ) + i];
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}
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if(PllFixDivider==1)
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{
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fprintf(stderr,"Use PLL Prediv\n");
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ana[1] |= (1 << 14); // use prediv means Frequency*2
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}
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else
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{
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ana[1]&=~(1<<14); // No use prediv means Frequency
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}
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for (int i = 3; i >= 0; i--)
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{
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gpioreg[(A2W_PLLC_ANA0 ) + i] = (0x5A << 24) | ana[i];
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usleep(100);
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}
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usleep(100);
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gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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usleep(100);
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@ -362,24 +396,11 @@ void clkgpio::SetAdvancedPllMode(bool Advanced)
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SetPllNumber(clk_pllc, 0); // Use PLL_C , Do not USE MASH which generates spurious
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//gpioreg[CM_PLLA] = 0x5A00022A; // Enable PllA_PER
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gpioreg[CM_PLLC] = 0x5A00022A; // Enable PllA_PER
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gpioreg[CM_PLLC] = 0x5A00022A; // Enable PllC_PER
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usleep(100);
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uint32_t ana[4];
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for (int i = 3; i >= 0; i--)
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{
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ana[i] = gpioreg[(A2W_PLLC_ANA0 ) + i];
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}
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ana[1]&=~(1<<14); // No use prediv means Frequency
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//ana[1] |= (1 << 14); // use prediv means Frequency*2
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for (int i = 3; i >= 0; i--)
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{
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gpioreg[(A2W_PLLC_ANA0 ) + i] = (0x5A << 24) | ana[i];
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}
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usleep(100);
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gpioreg[PLLC_CORE0] = 0x5A000000|(1<<8);//Disable
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gpioreg[PLLC_PER] = 0x5A000001; // Divisor
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usleep(100);
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