pi4 detection and CLKOSC according
This commit is contained in:
F5OEO
f5oeo
parent
a3611e265e
commit
2d2d854280
4 changed files with 140 additions and 41 deletions
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@ -701,10 +701,40 @@ void SimpleTestAtv(uint64_t Freq)
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}
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}
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void info(void)
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void info(uint64_t Freq)
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{
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generalgpio genpio;
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fprintf(stderr, "GPIOPULL =%x\n", genpio.gpioreg[GPPUDCLK0]);
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#define PULL_OFF 0
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#define PULL_DOWN 1
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#define PULL_UP 2
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/*genpio.gpioreg[GPPUD] = 0; //PULL_DOWN;
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usleep(150);
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genpio.gpioreg[GPPUDCLK0] = (1 << 4); //GPIO CLK is GPIO 4
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usleep(150);
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genpio.gpioreg[GPPUDCLK0] = (0); //GPIO CLK is GPIO 4
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*/
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//genpio.setpulloff(4);
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padgpio pad;
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pad.setlevel(7);
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clkgpio clk;
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clk.print_clock_tree();
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clk.SetPllNumber(clk_plld, 2);
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clk.enableclk(4);
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//clk.SetAdvancedPllMode(true);
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//clk.SetPLLMasterLoop(0,4,0);
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//clk.Setppm(+7.7);
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clk.SetCenterFrequency(Freq, 1000);
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double freqresolution = clk.GetFrequencyResolution();
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double RealFreq = clk.GetRealFrequency(0);
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fprintf(stderr, "Frequency resolution=%f Error freq=%f\n", freqresolution, RealFreq);
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int Deviation = 0;
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clk.SetFrequency(000);
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sleep(10);
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clk.disableclk(4);
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}
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@ -744,5 +774,5 @@ int main(int argc, char *argv[])
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//SimpleTestbpsk(Freq);
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//SimpleTestAtv(Freq);
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info();
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info(Freq);
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}
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126
src/gpio.cpp
126
src/gpio.cpp
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@ -31,7 +31,8 @@ extern "C" {
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gpio::gpio(uint32_t base, uint32_t len)
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{
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gpioreg = (uint32_t *)mapmem(base, len);
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gpioreg = (uint32_t *)mapmem(GetPeripheralBase()+base, len);
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gpiolen=len;
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}
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@ -41,40 +42,84 @@ gpio::~gpio()
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unmapmem((void*)gpioreg,gpiolen);
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}
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uint32_t get_hwbase(void)
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{
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const char *ranges_file = "/proc/device-tree/soc/ranges";
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uint8_t ranges[12];
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FILE *fd;
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uint32_t ret = 0;
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memset(ranges, 0, sizeof(ranges));
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if ((fd = fopen(ranges_file, "rb")) == NULL)
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{
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printf("Can't open '%s'\n", ranges_file);
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}
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else if (fread(ranges, 1, sizeof(ranges), fd) >= 8)
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{
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ret = (ranges[4] << 24) |
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(ranges[5] << 16) |
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(ranges[6] << 8) |
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(ranges[7] << 0);
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if (!ret)
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ret = (ranges[8] << 24) |
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(ranges[9] << 16) |
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(ranges[10] << 8) |
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(ranges[11] << 0);
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if ((ranges[0] != 0x7e) ||
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(ranges[1] != 0x00) ||
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(ranges[2] != 0x00) ||
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(ranges[3] != 0x00) ||
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((ret != 0x20000000) && (ret != 0x3f000000) && (ret != 0xfe000000)))
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{
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printf("Unexpected ranges data (%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x)\n",
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ranges[0], ranges[1], ranges[2], ranges[3],
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ranges[4], ranges[5], ranges[6], ranges[7],
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ranges[8], ranges[9], ranges[10], ranges[11]);
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ret = 0;
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}
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}
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else
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{
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printf("Ranges data too short\n");
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}
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fclose(fd);
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return ret;
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}
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uint32_t gpio::GetPeripheralBase()
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{
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RASPBERRY_PI_INFO_T info;
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uint32_t BCM2708_PERI_BASE = bcm_host_get_peripheral_address();
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dbg_printf(1,"Peri Base = %x SDRAM %x\n",bcm_host_get_peripheral_address(),bcm_host_get_sdram_address());
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uint32_t BCM2708_PERI_BASE =bcm_host_get_peripheral_address();
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dbg_printf(1,"Peri Base = %x SDRAM %x\n",/*get_hwbase()*/bcm_host_get_peripheral_address(),bcm_host_get_sdram_address());
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if(BCM2708_PERI_BASE==0xFE000000) // Fixme , could be inspect without this hardcoded value
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{
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pi_is_2711=true; //Rpi4
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XOSC_FREQUENCY=54000000;
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}
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if(BCM2708_PERI_BASE==0)
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{
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dbg_printf(0,"Unknown peripheral base, swith to PI4 \n");
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BCM2708_PERI_BASE=0xfe000000;
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XOSC_FREQUENCY=54000000;
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pi_is_2711=true;
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}
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/*
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if (getRaspberryPiInformation(&info) > 0)
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{
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if (info.peripheralBase == RPI_BROADCOM_2835_PERIPHERAL_BASE)
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{
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BCM2708_PERI_BASE = info.peripheralBase;
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}
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if ((info.peripheralBase == RPI_BROADCOM_2836_PERIPHERAL_BASE) || (info.peripheralBase == RPI_BROADCOM_2837_PERIPHERAL_BASE))
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{
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BCM2708_PERI_BASE = info.peripheralBase;
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}
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}*/
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if(pi_is_2711)
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dbg_printf(1,"Running on Pi4\n");
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return BCM2708_PERI_BASE;
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}
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//******************** DMA Registers ***************************************
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dmagpio::dmagpio() : gpio(GetPeripheralBase() + DMA_BASE, DMA_LEN)
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dmagpio::dmagpio() : gpio( DMA_BASE, DMA_LEN)
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{
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}
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// ***************** CLK Registers *****************************************
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clkgpio::clkgpio() : gpio(GetPeripheralBase() + CLK_BASE, CLK_LEN)
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clkgpio::clkgpio() : gpio(CLK_BASE, CLK_LEN)
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{
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SetppmFromNTP();
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padgpio level;
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@ -118,21 +163,21 @@ uint64_t clkgpio::GetPllFrequency(int PllNo)
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Freq = XOSC_FREQUENCY;
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break;
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case clk_plla:
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Freq = XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLA_CTRL] & 0x3ff) + XOSC_FREQUENCY * (uint64_t)gpioreg[PLLA_FRAC] / (1 << 20);
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Freq = (XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLA_CTRL] & 0x3ff) + XOSC_FREQUENCY * (uint64_t)gpioreg[PLLA_FRAC] / (1 << 20))/(2*(gpioreg[PLLA_CTRL] >> 12)&0x7);
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break;
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//case clk_pllb:Freq=XOSC_FREQUENCY*((uint64_t)gpioreg[PLLB_CTRL]&0x3ff) +XOSC_FREQUENCY*(uint64_t)gpioreg[PLLB_FRAC]/(1<<20);break;
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case clk_pllc:
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Freq = XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLC_CTRL] & 0x3ff) + XOSC_FREQUENCY * (uint64_t)gpioreg[PLLC_FRAC] / (1 << 20);
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Freq = (XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLC_CTRL] & 0x3ff) + XOSC_FREQUENCY * (uint64_t)gpioreg[PLLC_FRAC] / (1 << 20))/(2*(gpioreg[PLLC_CTRL] >> 12)&0x7) ;
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break;
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case clk_plld:
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Freq = (XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLD_CTRL] & 0x3ff) + (XOSC_FREQUENCY * (uint64_t)gpioreg[PLLD_FRAC]) / (1 << 20)) / (gpioreg[PLLD_PER] >> 1);
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Freq =( (XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLD_CTRL] & 0x3ff) + (XOSC_FREQUENCY * (uint64_t)gpioreg[PLLD_FRAC]) / (1 << 20)) / (2*gpioreg[PLLD_PER] >> 1))/((gpioreg[PLLD_CTRL] >> 12)&0x7) ;
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break;
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case clk_hdmi:
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Freq = XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLH_CTRL] & 0x3ff) + XOSC_FREQUENCY * (uint64_t)gpioreg[PLLH_FRAC] / (1 << 20);
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Freq =( XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLH_CTRL] & 0x3ff) + XOSC_FREQUENCY * (uint64_t)gpioreg[PLLH_FRAC] / (1 << 20))/(2*(gpioreg[PLLH_CTRL] >> 12)&0x7) ;
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break;
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}
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Freq=Freq*(1.0-clk_ppm*1e-6);
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dbg_printf(1, "Freq PLL no %d= %llu\n",PllNo, Freq);
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dbg_printf(1, "Pi4=%d Xosc = %llu Freq PLL no %d= %llu\n",pi_is_2711,XOSC_FREQUENCY,PllNo, Freq);
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return Freq;
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}
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@ -221,7 +266,8 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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#define MIN_PLL_RATE 200e6
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#define MIN_PLL_RATE_USE_PDIV 1500e6 //1700 works but some ticky breaks in clock..PLL should be at limit
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#define MAX_PLL_RATE 4e9
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#define XTAL_RATE 19.2e6
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#define XTAL_RATE XOSC_FREQUENCY
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//Pi4 seems 54Mhz
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double xtal_freq_recip = 1.0 / XTAL_RATE; // todo PPM correction
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int best_divider = 0;
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@ -631,7 +677,7 @@ void clkgpio::SetppmFromNTP()
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// ************************************** GENERAL GPIO *****************************************************
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generalgpio::generalgpio() : gpio(GetPeripheralBase() + GENERAL_BASE, GENERAL_LEN)
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generalgpio::generalgpio() : gpio(/*GetPeripheralBase() + */GENERAL_BASE, GENERAL_LEN)
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{
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}
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@ -653,18 +699,32 @@ int generalgpio::setmode(uint32_t gpio, uint32_t mode)
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int generalgpio::setpulloff(uint32_t gpio)
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{
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gpioreg[GPPUD]=0;
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usleep(150);
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gpioreg[GPPUDCLK0]=1<<gpio;
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usleep(150);
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gpioreg[GPPUDCLK0]=0;
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if(!pi_is_2711)
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{
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gpioreg[GPPUD]=0;
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usleep(150);
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gpioreg[GPPUDCLK0]=1<<gpio;
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usleep(150);
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gpioreg[GPPUDCLK0]=0;
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}
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else
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{
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uint32_t bits;
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uint32_t pull=0; // 0 OFF, 1 = UP, 2= DOWN
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int shift = (gpio & 0xf) << 1;
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bits = gpioreg[GPPUPPDN0 + (gpio>>4)];
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bits &= ~(3 << shift);
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bits |= (pull << shift);
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gpioreg[GPPUPPDN0 + (gpio>>4)] = bits;
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}
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return 0;
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}
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// ********************************** PWM GPIO **********************************
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pwmgpio::pwmgpio() : gpio(GetPeripheralBase() + PWM_BASE, PWM_LEN)
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pwmgpio::pwmgpio() : gpio(/*GetPeripheralBase() + */PWM_BASE, PWM_LEN)
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{
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gpioreg[PWM_CTL] = 0;
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@ -814,7 +874,7 @@ int pwmgpio::SetPrediv(int predivisor) //Mode should be only for SYNC or a Data
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// ********************************** PCM GPIO (I2S) **********************************
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pcmgpio::pcmgpio() : gpio(GetPeripheralBase() + PCM_BASE, PCM_LEN)
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pcmgpio::pcmgpio() : gpio(PCM_BASE, PCM_LEN)
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{
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gpioreg[PCM_CS_A] = 1; // Disable Rx+Tx, Enable PCM block
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}
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@ -899,7 +959,7 @@ int pcmgpio::SetPrediv(int predivisor) //Carefull we use a 10 fixe divisor for n
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// ********************************** PADGPIO (Amplitude) **********************************
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padgpio::padgpio() : gpio(GetPeripheralBase() + PADS_GPIO, PADS_GPIO_LEN)
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padgpio::padgpio() : gpio(PADS_GPIO, PADS_GPIO_LEN)
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{
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}
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17
src/gpio.h
17
src/gpio.h
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@ -7,7 +7,9 @@
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class gpio
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{
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public:
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bool pi_is_2711=false;
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uint64_t XOSC_FREQUENCY=19200000;
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public:
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volatile uint32_t *gpioreg = NULL;
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uint32_t gpiolen;
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@ -57,7 +59,7 @@ class dmagpio : public gpio
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//************************************ GENERAL GPIO ***************************************
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#define GENERAL_BASE (0x00200000)
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#define GENERAL_LEN 0xB4
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#define GENERAL_LEN 0xD0
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#define GPFSEL0 (0x00 / 4)
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#define GPFSEL1 (0x04 / 4)
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@ -66,6 +68,11 @@ class dmagpio : public gpio
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#define GPPUDCLK0 (0x98 / 4)
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#define GPPUDCLK1 (0x9C / 4)
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#define GPPUPPDN0 (0xBC/4)
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#define GPPUPPDN1 (0xC0/4)
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#define GPPUPPDN2 (0xC4/4)
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#define GPPUPPDN3 (0xC8/4)
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enum
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{
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fsel_input,
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@ -104,6 +111,8 @@ class generalgpio : public gpio
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#define GPCLK_DIV_2 (0x84 / 4)
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#define EMMCCLK_CNTL (0x1C0 / 4)
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#define EMMCCLK_DIV (0x1C4 / 4)
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#define CM_EMMC2CTL (0x1d0/4)
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#define CM_EMMC2DIV (0x1d4/4)
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#define CM_VPUCTL 0x008
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#define CM_VPUDIV 0x00c
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@ -246,8 +255,8 @@ class generalgpio : public gpio
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#define PLLH_STS (0x1660 / 4)
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#define XOSC_CTRL (0x1190 / 4)
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#define XOSC_FREQUENCY 19200000
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//#define XOSC_FREQUENCY 19200000
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//#define XOSC_FREQUENCY 54000000
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//Parent PLL
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enum
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{
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@ -41,7 +41,7 @@ phasedmasync::phasedmasync(uint64_t TuneFrequency,uint32_t SampleRateIn,int Numb
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clkgpio::SetAdvancedPllMode(true);
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clkgpio::ComputeBestLO(tunefreq,0); // compute PWM divider according to MasterPLL clkgpio::PllFixDivider
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double FloatMult=((double)(tunefreq)*clkgpio::PllFixDivider)/(double)(XOSC_FREQUENCY);
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double FloatMult=((double)(tunefreq)*clkgpio::PllFixDivider)/(double)(pwmgpio::XOSC_FREQUENCY);
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uint32_t freqctl = FloatMult*((double)(1<<20)) ;
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int IntMultiply= freqctl>>20; // Need to be calculated to have a center frequency
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freqctl&=0xFFFFF; // Fractionnal is 20bits
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