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simplify dma writting

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This commit is contained in:
F5OEO 2019-01-06 10:51:52 +00:00
parent d23e1fd8fc
commit 326d51cbbc
12 changed files with 469 additions and 740 deletions
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2
src/Makefile
View file

@ -4,7 +4,7 @@ LDFLAGS = -lm -lrt -lpthread
CCP = c++ CCP = c++
CC = cc CC = cc
librpitx: librpitx.h gpio.h gpio.cpp dma.h dma.cpp mailbox.c raspberry_pi_revision.c fmdmasync.h fmdmasync.cpp ngfmdmasync.h ngfmdmasync.cpp dsp.h dsp.cpp iqdmasync.h iqdmasync.cpp serialdmasync.h serialdmasync.cpp phasedmasync.h phasedmasync.cpp fskburst.h fskburst.cpp ookburst.cpp ookburst.h atv.h atv.cpp librpitx: librpitx.h gpio.h gpio.cpp dma.h dma.cpp mailbox.c raspberry_pi_revision.c fmdmasync.h fmdmasync.cpp ngfmdmasync.h ngfmdmasync.cpp dsp.h dsp.cpp iqdmasync.h iqdmasync.cpp serialdmasync.h serialdmasync.cpp phasedmasync.h phasedmasync.cpp fskburst.h fskburst.cpp ookburst.cpp ookburst.h atv.h atv.cpp util.h
$(CC) $(CFLAGS) -c -o mailbox.o mailbox.c $(CC) $(CFLAGS) -c -o mailbox.o mailbox.c
$(CC) $(CFLAGS) -c -o raspberry_pi_revision.o raspberry_pi_revision.c $(CC) $(CFLAGS) -c -o raspberry_pi_revision.o raspberry_pi_revision.c
$(CCP) $(CXXFLAGS) -c dsp.cpp iqdmasync.cpp ngfmdmasync.cpp fmdmasync.cpp dma.cpp gpio.cpp serialdmasync.cpp phasedmasync.cpp amdmasync.h amdmasync.cpp fskburst.cpp ookburst.cpp atv.cpp $(CCP) $(CXXFLAGS) -c dsp.cpp iqdmasync.cpp ngfmdmasync.cpp fmdmasync.cpp dma.cpp gpio.cpp serialdmasync.cpp phasedmasync.cpp amdmasync.h amdmasync.cpp fskburst.cpp ookburst.cpp atv.cpp

28
src/amdmasync.cpp
View file

@ -72,39 +72,17 @@ void amdmasync::SetDmaAlgo()
//@0 //@0
//Set Amplitude by writing to PADS //Set Amplitude by writing to PADS
cbp->info = 0;//BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp,samplecnt*registerbysample,dma_pad,1);
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
cbp->dst = 0x7E000000+(PADS_GPIO_0<<2)+PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++; cbp++;
//@1 //@1
//Set Amplitude to FSEL for amplitude=0 //Set Amplitude to FSEL for amplitude=0
cbp->info = 0;//BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp,samplecnt*registerbysample+1,dma_fsel,1);
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample+1]);
cbp->dst = 0x7E000000 + (GPFSEL0<<2)+GENERAL_BASE;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++; cbp++;
// Delay // Delay
if(syncwithpwm) SetEasyCB(cbp,samplecnt*registerbysample,syncwithpwm?dma_pwm:dma_pcm,1);
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if(syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO<<2) + PWM_BASE ;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A<<2) + PCM_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
//fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next);
cbp++; cbp++;
} }

270
src/atv.cpp
View file

@ -77,6 +77,10 @@ void atv::SetDmaAlgo()
uint32_t level1 = mem_virt_to_phys(&usermem[(usermemsize - 2)]); uint32_t level1 = mem_virt_to_phys(&usermem[(usermemsize - 2)]);
uint32_t level4 = mem_virt_to_phys(&usermem[(usermemsize - 3)]); uint32_t level4 = mem_virt_to_phys(&usermem[(usermemsize - 3)]);
uint32_t index_level0 = usermemsize - 1;
uint32_t index_level1 = usermemsize - 2;
uint32_t index_level4 = usermemsize - 3;
int shortsync_0 = 2; int shortsync_0 = 2;
int shortsync_1 = 30; int shortsync_1 = 30;
@ -96,267 +100,60 @@ void atv::SetDmaAlgo()
//2us 0,30us 1 //2us 0,30us 1
//@0 //@0
//SYNC preegalisation 2us //SYNC preegalisation 2us
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp++, index_level0, dma_pad, 1);
cbp->src = level0; //Amp 0 SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, shortsync_0);
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay
if (syncwithpwm)
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4 * shortsync_0; //2us
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
//SYNC preegalisation 30us //SYNC preegalisation 30us
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp++, index_level1, dma_pad, 1);
cbp->src = level1; //Amp 1 SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, shortsync_1);
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay
if (syncwithpwm)
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4 * shortsync_1; //30us
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
} }
//SYNC top trame 5*4*2frameCB //SYNC top trame 5*4*2frameCB
for (int i = 0; i < 5; i++) for (int i = 0; i < 5; i++)
{ {
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp++, index_level0, dma_pad, 1);
cbp->src = level0; //Amp 0 27us SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, longsync_0);
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay SetEasyCB(cbp++, index_level1, dma_pad, 1);
if (syncwithpwm) SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, longsync_1);
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4 * longsync_0; //27us
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
cbp->src = level1; //Amp 1 5us
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay
if (syncwithpwm)
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4 * longsync_1; //5us
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
} }
//postegalisation ; copy paste from preegalisation //postegalisation ; copy paste from preegalisation
//5*4*2CB //5*4*2CB
for (int i = 0; i < 5 /*-i*/; i++) for (int i = 0; i < 5 + frame; i++)
{ {
//2us 0,30us 1 //2us 0,30us 1
//@0 //@0
//SYNC preegalisation 2us //SYNC preegalisation 2us
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp++, index_level0, dma_pad, 1);
cbp->src = level0; //Amp 0 SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, shortsync_0);
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay
if (syncwithpwm)
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4 * shortsync_0; //2us
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
//SYNC preegalisation 30us //SYNC preegalisation 30us
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp++, index_level1, dma_pad, 1);
cbp->src = level1; //Amp 1 SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, shortsync_1);
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay
if (syncwithpwm)
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4 * shortsync_1; //30us
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
} }
//(304+305)*(4+52*2+2)CB //(304+305)*(4+52*2+2)CB
for (int line = 0; line < 305 /* 317 + frame*/; line++) for (int line = 0; line < 305 /* 317 + frame*/; line++)
{ {
//@0 //@0
//SYNC 0/ 5us //SYNC 0/ 5us
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp++, index_level0, dma_pad, 1);
cbp->src = level0; //Amp 0 SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, normalsync_0);
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay
if (syncwithpwm)
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4 * normalsync_0; //4us
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
//@0
//SYNC 1/ 5us //SYNC 1/ 5us
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp++, index_level1, dma_pad, 1);
cbp->src = level1; //Amp 1 SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, normalsync_1);
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay
if (syncwithpwm)
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4 * normalsync_1; //5us;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
for (uint32_t samplecnt = 0; samplecnt < 52; samplecnt++) //52 us for (uint32_t samplecnt = 0; samplecnt < 52; samplecnt++) //52 us
{ {
//sampletab[samplecnt * registerbysample] = (0x5A << 24) + (3 & 0x7) + (1 << 4) + (0 << 3); // Amplitude PAD SetEasyCB(cbp++, samplecnt + line * 52 + frame * 312 * 52, dma_pad, 1);
//@0 SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, 1);
//DATA IN / 1us
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
//if(line<20) cbp->src=level1;
//if((line>=20)&&(line<40)) cbp->src=level4;
//if(line>=20)
cbp->src = mem_virt_to_phys(&usermem[samplecnt + line * 52 + frame * 312 * 52]);
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay
if (syncwithpwm)
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4; //1us
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
} }
//FRONT PORSH //FRONT PORSH
//SYNC 2us //SYNC 2us
cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp++, index_level1, dma_pad, 1);
cbp->src = level1; //Amp 1 SetEasyCB(cbp++, 0, syncwithpwm ? dma_pwm : dma_pcm, frontsync_1);
cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay
if (syncwithpwm)
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP | BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if (syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
cbp->length = 4 * frontsync_1; //2us
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
} }
} }
cbp--; cbp--;
@ -371,22 +168,11 @@ void atv::SetFrame(unsigned char *Luminance, size_t Lines)
for (size_t x = 0; x < 52; x++) for (size_t x = 0; x < 52; x++)
{ {
int AmplitudePAD = (Luminance[i * 52 + x] / 255.0) * 6.0 + 1; //1 to 7 int AmplitudePAD = (Luminance[i * 52 + x] / 255.0) * 6.0 + 1; //1 to 7
// usermem[i* 52 + x] = (0x5A << 24) + (AmplitudePAD & 0x7) + (1 << 4) + (0 << 3); // Amplitude PAD
if (i % 2 == 0) // First field if (i % 2 == 0) // First field
usermem[i * 52 / 2 + x] = (0x5A << 24) + (AmplitudePAD & 0x7) + (1 << 4) + (0 << 3); // Amplitude PAD usermem[i * 52 / 2 + x] = (0x5A << 24) + (AmplitudePAD & 0x7) + (1 << 4) + (0 << 3); // Amplitude PAD
else else
usermem[(i - 1) * 52 / 2 + x + 52 * 312] = (0x5A << 24) + (AmplitudePAD & 0x7) + (1 << 4) + (0 << 3); // Amplitude PAD usermem[(i - 1) * 52 / 2 + x + 52 * 312] = (0x5A << 24) + (AmplitudePAD & 0x7) + (1 << 4) + (0 << 3); // Amplitude PAD
}
}
/*for (size_t x = 0; x < 52; x++)
{
int AmplitudePAD = (Luminance[i * 52 + x]/255.0) * 6 + 1; //1 to 7
if (i % 2 == 0) // First field
usermem[i * 52 / 2 + x] = (0x5A << 24) + (AmplitudePAD & 0x7) + (1 << 4) + (0 << 3); // Amplitude PAD
else //second field
usermem[i * 52 / 2 + Lines / 2 + x] = (0x5A << 24) + (AmplitudePAD & 0x7) + (1 << 4) + (0 << 3); // Amplitude PAD
}
*/
} }
} }

28
src/dma.cpp
View file

@ -18,6 +18,7 @@ This program is free software: you can redistribute it and/or modify
#include "dma.h" #include "dma.h"
#include "stdio.h" #include "stdio.h"
#include "util.h"
extern "C" extern "C"
{ {
@ -166,6 +167,33 @@ bool dma::isunderflow()
return ((dma_reg.gpioreg[DMA_CS+channel*0x40]&DMA_CS_INT)>0); return ((dma_reg.gpioreg[DMA_CS+channel*0x40]&DMA_CS_INT)>0);
} }
bool dma::SetCB(dma_cb_t *cbp,uint32_t dma_flag,uint32_t src,uint32_t dst,uint32_t repeat)
{
cbp->info = dma_flag;
cbp->src = src;
cbp->dst = dst;
cbp->length = 4*repeat;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
return true;
}
bool dma::SetEasyCB(dma_cb_t *cbp,uint32_t index,dma_common_reg dst,uint32_t repeat)
{
uint32_t flag=BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP;
uint32_t src=mem_virt_to_phys(&usermem[index]);
switch(dst)
{
case dma_pllc_frac :break;
case dma_fsel:break;
case dma_pad:break;
case dma_pwm : flag|=BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);break;
case dma_pcm : flag|=BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);break;
}
SetCB(cbp,flag,src,dst,repeat);
return true;
}
//**************************************** BUFFER DMA ******************************************************** //**************************************** BUFFER DMA ********************************************************
bufferdma::bufferdma(int Channel,uint32_t tbuffersize,uint32_t tcbbysample,uint32_t tregisterbysample):dma(Channel,tbuffersize*tcbbysample,tbuffersize*tregisterbysample) bufferdma::bufferdma(int Channel,uint32_t tbuffersize,uint32_t tcbbysample,uint32_t tregisterbysample):dma(Channel,tbuffersize*tcbbysample,tbuffersize*tregisterbysample)
{ {

23
src/dma.h
View file

@ -1,8 +1,9 @@
#ifndef DEF_DMA #ifndef DEF_DMA
#define DEF_DMA #define DEF_DMA
#include "stdint.h" #include "stdint.h"
#include "gpio.h" #include "gpio.h"
#include "util.h"
// ---- Memory allocating defines // ---- Memory allocating defines
// https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface // https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
#define MEM_FLAG_DISCARDABLE (1 << 0) /* can be resized to 0 at any time. Use for cached data */ #define MEM_FLAG_DISCARDABLE (1 << 0) /* can be resized to 0 at any time. Use for cached data */
@ -20,7 +21,6 @@
#define BCM2708_DMA_NO_WIDE_BURSTS (1 << 26) #define BCM2708_DMA_NO_WIDE_BURSTS (1 << 26)
#define BCM2708_DMA_WAIT_RESP (1 << 3) #define BCM2708_DMA_WAIT_RESP (1 << 3)
#define BCM2708_DMA_D_DREQ (1 << 6) #define BCM2708_DMA_D_DREQ (1 << 6)
#define BCM2708_DMA_PER_MAP(x) ((x) << 16) #define BCM2708_DMA_PER_MAP(x) ((x) << 16)
#define BCM2708_DMA_END (1 << 1) #define BCM2708_DMA_END (1 << 1)
@ -41,23 +41,25 @@
#define DREQ_SPI_SLAVE_TX 8 #define DREQ_SPI_SLAVE_TX 8
#define DREQ_SPI_SLAVE_RX 9 #define DREQ_SPI_SLAVE_RX 9
class dma class dma
{ {
protected: protected:
struct { struct
{
int handle; /* From mbox_open() */ int handle; /* From mbox_open() */
unsigned mem_ref; /* From mem_alloc() */ unsigned mem_ref; /* From mem_alloc() */
unsigned bus_addr; /* From mem_lock() */ unsigned bus_addr; /* From mem_lock() */
uint8_t *virt_addr; /* From mapmem() */ uint8_t *virt_addr; /* From mapmem() */
} mbox; } mbox;
typedef struct { typedef struct
{
uint32_t info, src, dst, length, uint32_t info, src, dst, length,
stride, next, pad[2]; stride, next, pad[2];
} dma_cb_t; //8*4=32 bytes } dma_cb_t; //8*4=32 bytes
typedef struct { typedef struct
{
uint8_t *virtaddr; uint8_t *virtaddr;
uint32_t physaddr; uint32_t physaddr;
} page_map_t; } page_map_t;
@ -72,7 +74,6 @@ class dma
uint32_t mem_flag; //Cache or not depending on Rpi1 or 2/3 uint32_t mem_flag; //Cache or not depending on Rpi1 or 2/3
uint32_t dram_phys_base; uint32_t dram_phys_base;
public: public:
dma_cb_t *cbarray; dma_cb_t *cbarray;
uint32_t cbsize; uint32_t cbsize;
@ -90,16 +91,13 @@ class dma
int getcbposition(); int getcbposition();
bool isrunning(); bool isrunning();
bool isunderflow(); bool isunderflow();
bool SetCB(dma_cb_t *cbp, uint32_t dma_flag, uint32_t src, uint32_t dst, uint32_t repeat);
bool SetEasyCB(dma_cb_t *cbp, uint32_t index, dma_common_reg dst, uint32_t repeat);
}; };
#define PHYSICAL_BUS 0x7E000000
class bufferdma : public dma class bufferdma : public dma
{ {
protected: protected:
uint32_t current_sample; uint32_t current_sample;
uint32_t last_sample; uint32_t last_sample;
uint32_t sample_available; uint32_t sample_available;
@ -116,6 +114,5 @@ class bufferdma:public dma
int GetBufferAvailable(); int GetBufferAvailable();
int GetUserMemIndex(); int GetUserMemIndex();
int PushSample(int Index); int PushSample(int Index);
}; };
#endif #endif

56
src/gpio.h
View file

@ -3,7 +3,7 @@
#include "stdint.h" #include "stdint.h"
#include <cstdio> #include <cstdio>
#define PHYSICAL_BUS 0x7E000000
class gpio class gpio
{ {
@ -16,7 +16,6 @@ class gpio
uint32_t GetPeripheralBase(); uint32_t GetPeripheralBase();
}; };
#define DMA_BASE (0x00007000) #define DMA_BASE (0x00007000)
#define DMA_LEN 0xF00 #define DMA_LEN 0xF00
@ -53,8 +52,6 @@ class dmagpio:public gpio
public: public:
dmagpio(); dmagpio();
}; };
//************************************ GENERAL GPIO *************************************** //************************************ GENERAL GPIO ***************************************
@ -69,7 +66,17 @@ class dmagpio:public gpio
#define GPPUDCLK0 (0x98 / 4) #define GPPUDCLK0 (0x98 / 4)
#define GPPUDCLK1 (0x9C / 4) #define GPPUDCLK1 (0x9C / 4)
enum {fsel_input,fsel_output,fsel_alt5,fsel_alt4,fsel_alt0,fsel_alt1,fsel_alt2,fsel_alt3}; enum
{
fsel_input,
fsel_output,
fsel_alt5,
fsel_alt4,
fsel_alt0,
fsel_alt1,
fsel_alt2,
fsel_alt3
};
class generalgpio : public gpio class generalgpio : public gpio
{ {
@ -170,7 +177,6 @@ class generalgpio:public gpio
#define CM_EMMCCTL 0x1c0 #define CM_EMMCCTL 0x1c0
#define CM_EMMCDIV 0x1c4 #define CM_EMMCDIV 0x1c4
#define CM_LOCK (0x114 / 4) #define CM_LOCK (0x114 / 4)
#define CM_LOCK_FLOCKH (1 << 12) #define CM_LOCK_FLOCKH (1 << 12)
#define CM_LOCK_FLOCKD (1 << 11) #define CM_LOCK_FLOCKD (1 << 11)
@ -195,8 +201,6 @@ class generalgpio:public gpio
#define CM_PLLH (0x110 / 4) #define CM_PLLH (0x110 / 4)
#define CM_PLLB (0x170 / 4) #define CM_PLLB (0x170 / 4)
#define A2W_PLLA_ANA0 (0x1010 / 4) #define A2W_PLLA_ANA0 (0x1010 / 4)
#define A2W_PLLC_ANA0 (0x1030 / 4) #define A2W_PLLC_ANA0 (0x1030 / 4)
#define A2W_PLLD_ANA0 (0x1050 / 4) #define A2W_PLLD_ANA0 (0x1050 / 4)
@ -245,7 +249,17 @@ class generalgpio:public gpio
#define XOSC_FREQUENCY 19200000 #define XOSC_FREQUENCY 19200000
//Parent PLL //Parent PLL
enum {clk_gnd,clk_osc,clk_debug0,clk_debug1,clk_plla,clk_pllc,clk_plld,clk_hdmi}; enum
{
clk_gnd,
clk_osc,
clk_debug0,
clk_debug1,
clk_plla,
clk_pllc,
clk_plld,
clk_hdmi
};
class clkgpio : public gpio class clkgpio : public gpio
{ {
@ -257,6 +271,7 @@ class clkgpio:public gpio
uint64_t CentralFrequency = 0; uint64_t CentralFrequency = 0;
generalgpio gengpio; generalgpio gengpio;
double clk_ppm = 0; double clk_ppm = 0;
public: public:
int PllFixDivider = 8; //Fix divider from the master clock in advanced mode int PllFixDivider = 8; //Fix divider from the master clock in advanced mode
@ -280,12 +295,8 @@ class clkgpio:public gpio
void Setppm(double ppm); void Setppm(double ppm);
void SetppmFromNTP(); void SetppmFromNTP();
void SetPLLMasterLoop(int Ki, int Kp, int Ka); void SetPLLMasterLoop(int Ki, int Kp, int Ka);
}; };
//************************************ PWM GPIO *************************************** //************************************ PWM GPIO ***************************************
#define PWM_BASE (0x0020C000) #define PWM_BASE (0x0020C000)
@ -300,7 +311,6 @@ class clkgpio:public gpio
#define PWMCLK_CNTL (40) // Clk register #define PWMCLK_CNTL (40) // Clk register
#define PWMCLK_DIV (41) // Clk register #define PWMCLK_DIV (41) // Clk register
#define PWMCTL_MSEN2 (1 << 15) #define PWMCTL_MSEN2 (1 << 15)
#define PWMCTL_USEF2 (1 << 13) #define PWMCTL_USEF2 (1 << 13)
#define PWMCTL_RPTL2 (1 << 10) #define PWMCTL_RPTL2 (1 << 10)
@ -316,7 +326,12 @@ class clkgpio:public gpio
#define PWMCTL_PWEN1 (1 << 0) #define PWMCTL_PWEN1 (1 << 0)
#define PWMDMAC_ENAB (1 << 31) #define PWMDMAC_ENAB (1 << 31)
#define PWMDMAC_THRSHLD ((15 << 8) | (15 << 0)) #define PWMDMAC_THRSHLD ((15 << 8) | (15 << 0))
enum pwmmode{pwm1pin,pwm2pin,pwm1pinrepeat}; enum pwmmode
{
pwm1pin,
pwm2pin,
pwm1pinrepeat
};
class pwmgpio : public gpio class pwmgpio : public gpio
{ {
@ -329,6 +344,7 @@ class pwmgpio:public gpio
bool ModulateFromMasterPLL = false; bool ModulateFromMasterPLL = false;
int ModePwm = pwm1pin; int ModePwm = pwm1pin;
generalgpio gengpio; generalgpio gengpio;
public: public:
pwmgpio(); pwmgpio();
~pwmgpio(); ~pwmgpio();
@ -376,7 +392,6 @@ class pcmgpio:public gpio
uint64_t GetPllFrequency(int PllNo); uint64_t GetPllFrequency(int PllNo);
int SetFrequency(uint64_t Frequency); int SetFrequency(uint64_t Frequency);
int ComputePrediv(uint64_t Frequency); int ComputePrediv(uint64_t Frequency);
}; };
//******************************* PAD GPIO (Amplitude) *********************************** //******************************* PAD GPIO (Amplitude) ***********************************
@ -396,4 +411,13 @@ class padgpio:public gpio
int setlevel(int level); int setlevel(int level);
}; };
enum dma_common_reg
{
dma_pllc_frac = 0x7E000000 + (PLLC_FRAC << 2) + CLK_BASE,
dma_pwm = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE,
dma_pcm = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE,
dma_fsel = 0x7E000000 + (GPFSEL0 << 2) + GENERAL_BASE,
dma_pad = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO
};
#endif #endif

43
src/iqdmasync.cpp
View file

@ -81,55 +81,20 @@ void iqdmasync::SetDmaAlgo()
for (uint32_t samplecnt = 0; samplecnt < buffersize; samplecnt++) for (uint32_t samplecnt = 0; samplecnt < buffersize; samplecnt++)
{ {
SetEasyCB(cbp,samplecnt*registerbysample+1,dma_pad,1);
//@0
//Set Amplitude by writing to PADS
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample+1]);
cbp->dst = 0x7E000000+(PADS_GPIO_0<<2)+PADS_GPIO;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++; cbp++;
//@2 Write a frequency sample : Order of DMA CS influence maximum rate : here 0,2,1 is the best : why !!!!!! //@2 Write a frequency sample : Order of DMA CS influence maximum rate : here 0,2,1 is the best : why !!!!!!
SetEasyCB(cbp,samplecnt*registerbysample,dma_pllc_frac,1);
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
cbp->dst = 0x7E000000 + (PLLC_FRAC<<2) + CLK_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
//fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next);
cbp++; cbp++;
//@1 //@1
//Set Amplitude to FSEL for amplitude=0 //Set Amplitude to FSEL for amplitude=0
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp,samplecnt*registerbysample+2,dma_fsel,1);
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample+2]);
cbp->dst = 0x7E000000 + (GPFSEL0<<2)+GENERAL_BASE;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++; cbp++;
//@3 Delay //@3 Delay
if(syncwithpwm) SetEasyCB(cbp,samplecnt*registerbysample,syncwithpwm?dma_pwm:dma_pcm,1);
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info =BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(&usermem[(samplecnt+1)*registerbysample]);//mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if(syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO<<2) + PWM_BASE ;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A<<2) + PCM_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
//fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next); //fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next);
cbp++; cbp++;

34
src/ngfmdmasync.cpp
View file

@ -74,31 +74,12 @@ void ngfmdmasync::SetDmaAlgo()
// Write a frequency sample // Write a frequency sample
SetEasyCB(cbp,samplecnt*registerbysample,dma_pllc_frac,1);
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
cbp->dst = 0x7E000000 + (PLLC_FRAC<<2) + CLK_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
//fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next);
cbp++; cbp++;
// Delay // Delay
if(syncwithpwm) SetEasyCB(cbp,samplecnt*registerbysample,syncwithpwm?dma_pwm:dma_pcm,1);
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if(syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO<<2) + PWM_BASE ;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A<<2) + PCM_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
//fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next);
cbp++; cbp++;
} }
@ -119,7 +100,7 @@ void ngfmdmasync::SetFrequencySample(uint32_t Index,float Frequency)
void ngfmdmasync::SetFrequencySamples(float *sample,size_t Size) void ngfmdmasync::SetFrequencySamples(float *sample,size_t Size)
{ {
size_t NbWritten=0; size_t NbWritten=0;
int OSGranularity=100; int OSGranularity=200;
long int start_time; long int start_time;
long time_difference=0; long time_difference=0;
@ -133,19 +114,20 @@ void ngfmdmasync::SetFrequencySamples(float *sample,size_t Size)
int TimeToSleep=1e6*((int)buffersize*3/4-Available)/SampleRate-OSGranularity; // Sleep for theorically fill 3/4 of Fifo int TimeToSleep=1e6*((int)buffersize*3/4-Available)/SampleRate-OSGranularity; // Sleep for theorically fill 3/4 of Fifo
if(TimeToSleep>0) if(TimeToSleep>0)
{ {
//fprintf(stderr,"buffer size %d Available %d SampleRate %d Sleep %d\n",buffersize,Available,SampleRate,TimeToSleep); fprintf(stderr,"buffer size %d Available %d SampleRate %d Sleep %d\n",buffersize,Available,SampleRate,TimeToSleep);
usleep(TimeToSleep); usleep(TimeToSleep);
} }
else else
{ {
//fprintf(stderr,"No Sleep %d\n",TimeToSleep); fprintf(stderr,"No Sleep %d\n",TimeToSleep);
sched_yield(); sched_yield();
} }
clock_gettime(CLOCK_REALTIME, &gettime_now); clock_gettime(CLOCK_REALTIME, &gettime_now);
time_difference = gettime_now.tv_nsec - start_time; time_difference = gettime_now.tv_nsec - start_time;
if(time_difference<0) time_difference+=1E9; if(time_difference<0) time_difference+=1E9;
//fprintf(stderr,"Measure samplerate=%d\n",(int)((GetBufferAvailable()-Available)*1e9/time_difference)); int NewAvailable=GetBufferAvailable();
Available=GetBufferAvailable(); fprintf(stderr,"Newavailable %d Measure samplerate=%d\n",NewAvailable,(int)((GetBufferAvailable()-Available)*1e9/time_difference));
Available=NewAvailable;
int Index=GetUserMemIndex(); int Index=GetUserMemIndex();
int ToWrite=((int)Size-(int)NbWritten)<Available?Size-NbWritten:Available; int ToWrite=((int)Size-(int)NbWritten)<Available?Size-NbWritten:Available;

52
src/ookburst.cpp
View file

@ -61,69 +61,31 @@ This program is free software: you can redistribute it and/or modify
// PCM FIFO = 64 // PCM FIFO = 64
if(syncwithpwm) if(syncwithpwm)
{ {
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM); SetEasyCB(cbp++,0,dma_pwm,16+1);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
cbp->dst = 0x7E000000 + (PWM_FIFO<<2) + PWM_BASE ;
cbp->length = 4*(16+1);
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
} }
else else
{ {
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX); SetEasyCB(cbp++,0,dma_pcm,64+1);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed PCM
cbp->dst = 0x7E000000 + (PCM_FIFO_A<<2) + PCM_BASE ;
cbp->length = 4*(64+1);
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
//fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next);
cbp++;
} }
for (uint32_t samplecnt = 0; samplecnt < buffersize-2; samplecnt++) for (uint32_t samplecnt = 0; samplecnt < buffersize-2; samplecnt++)
{ {
//Set Amplitude to FSEL for amplitude=0 //Set Amplitude to FSEL for amplitude=0
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp++,samplecnt*registerbysample,dma_fsel,1);
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
cbp->dst = 0x7E000000 + (GPFSEL0<<2)+GENERAL_BASE;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
cbp++;
// Delay // Delay
if(syncwithpwm) SetEasyCB(cbp++,samplecnt*registerbysample,syncwithpwm?dma_pwm:dma_pcm,1);
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
else
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PCM_TX);
cbp->src = mem_virt_to_phys(cbarray); // Data is not important as we use it only to feed the PWM
if(syncwithpwm)
cbp->dst = 0x7E000000 + (PWM_FIFO<<2) + PWM_BASE ;
else
cbp->dst = 0x7E000000 + (PCM_FIFO_A<<2) + PCM_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
//fprintf(stderr,"cbp : sample %d pointer %p src %x dest %x next %x\n",samplecnt,cbp,cbp->src,cbp->dst,cbp->next);
cbp++;
} }
lastcbp=cbp; lastcbp=cbp;
// Last CBP before stopping : disable output // Last CBP before stopping : disable output
sampletab[buffersize*registerbysample-1]=(Originfsel & ~(7 << 12)) | (0 << 12); //Disable Clk sampletab[buffersize*registerbysample-1]=(Originfsel & ~(7 << 12)) | (0 << 12); //Disable Clk
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ; SetEasyCB(cbp,buffersize*registerbysample-1,dma_fsel,1);
cbp->src = mem_virt_to_phys(&usermem[(buffersize*registerbysample-1)]);
cbp->dst = 0x7E000000 + (GPFSEL0<<2)+GENERAL_BASE;
cbp->length = 4;
cbp->stride = 0;
cbp->next = 0; // Stop DMA cbp->next = 0; // Stop DMA
//fprintf(stderr,"Last cbp %p: src %x dest %x next %x\n",cbp,cbp->src,cbp->dst,cbp->next);
} }
void ookburst::SetSymbols(unsigned char *Symbols,uint32_t Size) void ookburst::SetSymbols(unsigned char *Symbols,uint32_t Size)
{ {

9
src/serialdmasync.cpp
View file

@ -62,14 +62,7 @@ void serialdmasync::SetDmaAlgo()
for (uint32_t samplecnt = 0; samplecnt < buffersize; samplecnt++) for (uint32_t samplecnt = 0; samplecnt < buffersize; samplecnt++)
{ {
SetEasyCB(cbp,samplecnt*registerbysample,dma_pwm,1);
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP |BCM2708_DMA_D_DREQ | BCM2708_DMA_PER_MAP(DREQ_PWM);
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
cbp->dst = 0x7E000000 + (PWM_FIFO<<2) + PWM_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);
//fprintf(stderr,"cbp : sample %x src %x dest %x next %x\n",samplecnt,cbp->src,cbp->dst,cbp->next);
cbp++; cbp++;
} }

14
src/util.h Normal file
View file

@ -0,0 +1,14 @@
#ifndef DEF_UTIL
#define DEF_UTIL
#include <stdio.h>
#include <stdarg.h>
void dbg_printf(const char *fmt, ...)
{
va_list args;
va_start(args, fmt);
vfprintf(stderr, fmt, args);
va_end(args);
}
#endif