Try ATV interlace
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F5OEO
parent
34d43bf441
commit
4ee1aa28dd
2 changed files with 72 additions and 26 deletions
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@ -644,15 +644,45 @@ void SimpleTestAtv(uint64_t Freq)
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int SR = 1000000;
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int FifoSize = 625*52;
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float samples[FifoSize];
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for(int j=0;j<625;j++)
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//Frame 0
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for(int j=0;j<312;j++)
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{
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if(j<160)
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{
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for(int i=0;i<52;i++) samples[i+j*52]=i/52.0;
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}
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else
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{
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for(int i=0;i<52;i++) samples[i+j*52]=0;
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}
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}
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//Frame 1
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for(int j=0;j<312;j++)
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{
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if(j<160)
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{
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for(int i=0;i<52;i++) samples[i+(j+312)*52]=i/52.0;
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}
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else
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{
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for(int i=0;i<52;i++) samples[i+(j+312)*52]=0;
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}
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}
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atv atvtest(Freq, SR, 14, 625);
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int Available = atvtest.GetBufferAvailable();
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int Index = atvtest.GetUserMemIndex();
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fprintf(stderr,"Available %d Index %d\n",Available,Index);
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atvtest.SetTvSamples(samples,FifoSize);
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while(running)
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{
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usleep(100000);
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//atvtest.SetTvSamples(samples,FifoSize);
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usleep(40000);
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}
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}
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62
src/atv.cpp
62
src/atv.cpp
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@ -35,7 +35,7 @@ atv::atv(uint64_t TuneFrequency, uint32_t SR, int Channel, uint32_t Lines) : buf
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clkgpio::SetCenterFrequency(TuneFrequency, SampleRate);
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clkgpio::SetFrequency(0);
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clkgpio::enableclk(4); // GPIO 4 CLK by default
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syncwithpwm = true;
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syncwithpwm = false;
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if (syncwithpwm)
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{
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@ -69,16 +69,27 @@ void atv::SetDmaAlgo()
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dma_cb_t *cbp = cbarray;
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int LineResolution = 625;
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uint32_t level0= mem_virt_to_phys(&usermem[(buffersize * registerbysample - 1)]);
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uint32_t level1= mem_virt_to_phys(&usermem[(buffersize * registerbysample - 2)]);
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int shortsync_0=2;
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int shortsync_1=30;
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int longsync_0=30;
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int longsync_1=2;
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int normalsync_0=4;
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int normalsync_1=8;
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for (int frame = 0; frame < 2; frame++)
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{
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//32us*5 or 6
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for (int i = 0; i < 5+frame; i++)
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//Preegalisation
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for (int i = 0; i < 6/*-frame*/; i++)
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{
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//2us 0,30us 1
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//@0
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//SYNC preegalisation 2us
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[(buffersize * registerbysample - 1)]); //Amp 0
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cbp->src = level0; //Amp 0
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cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
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cbp->length = 4;
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cbp->stride = 0;
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@ -95,14 +106,14 @@ void atv::SetDmaAlgo()
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cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
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else
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cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
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cbp->length = 4 * 2; //2us
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cbp->length = 4 * shortsync_0; //2us
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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//SYNC preegalisation 30us
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[(buffersize * registerbysample - 2)]); //Amp 1
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cbp->src = level1; //Amp 1
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cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
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cbp->length = 4;
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cbp->stride = 0;
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@ -119,7 +130,7 @@ void atv::SetDmaAlgo()
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cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
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else
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cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
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cbp->length = 4 * 30; //30us
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cbp->length = 4 * shortsync_1; //30us
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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@ -128,7 +139,7 @@ void atv::SetDmaAlgo()
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for (int i = 0; i < 5; i++)
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{
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[(buffersize * registerbysample - 1)]); //Amp 0 27us
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cbp->src = level0; //Amp 0 27us
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cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
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cbp->length = 4;
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cbp->stride = 0;
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@ -145,13 +156,13 @@ void atv::SetDmaAlgo()
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cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
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else
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cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
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cbp->length = 4 * 27; //27us
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cbp->length = 4 * longsync_0; //27us
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[(buffersize * registerbysample - 2)]); //Amp 1 5us
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cbp->src = level1; //Amp 1 5us
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cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
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cbp->length = 4;
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cbp->stride = 0;
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@ -168,19 +179,19 @@ void atv::SetDmaAlgo()
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cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
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else
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cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
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cbp->length = 4 * 5; //5us
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cbp->length = 4 * longsync_1; //5us
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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}
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//postegalisation ; copy paste from preegalisation
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for (int i = 0; i < 5; i++)
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for (int i = 0; i < 5/*-i*/; i++)
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{
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//2us 0,30us 1
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//@0
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//SYNC preegalisation 2us
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[(buffersize * registerbysample - 1)]); //Amp 0
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cbp->src = level0; //Amp 0
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cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
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cbp->length = 4;
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cbp->stride = 0;
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@ -197,14 +208,14 @@ void atv::SetDmaAlgo()
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cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
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else
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cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
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cbp->length = 4 * 2; //2us
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cbp->length = 4 * shortsync_0; //2us
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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//SYNC preegalisation 30us
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[(buffersize * registerbysample - 2)]); //Amp 1
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cbp->src = level1; //Amp 1
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cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
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cbp->length = 4;
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cbp->stride = 0;
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@ -221,19 +232,19 @@ void atv::SetDmaAlgo()
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cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
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else
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cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
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cbp->length = 4 * 30; //30us
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cbp->length = 4 * shortsync_1; //30us
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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}
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for (int line = 0; line < 305; line++)
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for (int line = 0; line < /*305*/304+frame; line++)
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{
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//@0
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//SYNC 0/ 5us
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[(buffersize * registerbysample - 1)]); //Amp 0
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cbp->src = level0; //Amp 0
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cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
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cbp->length = 4;
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cbp->stride = 0;
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@ -250,7 +261,7 @@ void atv::SetDmaAlgo()
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cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
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else
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cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
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cbp->length = 4 * 4; //5us
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cbp->length = 4 * normalsync_0; //4us
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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@ -258,7 +269,7 @@ void atv::SetDmaAlgo()
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//@0
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//SYNC 1/ 5us
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[(buffersize * registerbysample - 2)]); //Amp 1
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cbp->src = level1; //Amp 1
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cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
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cbp->length = 4;
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cbp->stride = 0;
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@ -275,7 +286,7 @@ void atv::SetDmaAlgo()
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cbp->dst = 0x7E000000 + (PWM_FIFO << 2) + PWM_BASE;
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else
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cbp->dst = 0x7E000000 + (PCM_FIFO_A << 2) + PCM_BASE;
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cbp->length = 4 * 6; //5us;
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cbp->length = 4 * normalsync_1; //5us;
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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@ -286,7 +297,11 @@ void atv::SetDmaAlgo()
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//@0
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//DATA IN / 1us
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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cbp->src = mem_virt_to_phys(&usermem[samplecnt * registerbysample]); //Amp 1
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if(line<10) //remove 10 lines
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cbp->src=level1;
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else
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cbp->src = mem_virt_to_phys(&usermem[samplecnt * registerbysample+frame*312*registerbysample]); //Amp 1
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cbp->dst = 0x7E000000 + (PADS_GPIO_0 << 2) + PADS_GPIO;
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cbp->length = 4;
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cbp->stride = 0;
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@ -308,6 +323,7 @@ void atv::SetDmaAlgo()
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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}
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/*
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//FRONT PORSH
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//SYNC 2us
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cbp->info = 0; //BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
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@ -331,7 +347,7 @@ void atv::SetDmaAlgo()
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cbp->length = 4 * 2; //2us
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cbp->stride = 0;
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cbp->next = mem_virt_to_phys(cbp + 1);
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cbp++;
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cbp++;*/
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}
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}
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cbp--;
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