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Move to PLLC because PLLA used by openvg

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This commit is contained in:
F5OEO 2018-10-03 14:05:01 +00:00
parent 3da98b2e0f
commit 73f0ba145b
7 changed files with 130 additions and 49 deletions
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49
app/testrpitx.cpp
View file

@ -48,7 +48,7 @@ void SimpleTest(uint64_t Freq)
clkgpio clk;
clk.print_clock_tree();
clk.SetPllNumber(clk_plla,0);
clk.SetPllNumber(clk_pllc,0);
//clk.SetAdvancedPllMode(true);
//clk.SetPLLMasterLoop(0,4,0);
@ -189,41 +189,26 @@ void SimpleTestbpsk(uint64_t Freq)
clkgpio clk;
clk.print_clock_tree();
int SR=100000;
int FifoSize=1024;
int SR=250000;
int FifoSize=10000;
int NumberofPhase=2;
phasedmasync biphase(Freq,SR,NumberofPhase,14,FifoSize);
padgpio pad;
pad.setlevel(7);
int lastphase=0;
#define BURST_SIZE 100
int PhaseBuffer[BURST_SIZE];
while(running)
{
//usleep(FifoSize*1000000.0*1.0/(8.0*SR));
usleep(10);
int Available=biphase.GetBufferAvailable();
if(Available>256)
{
int Index=biphase.GetUserMemIndex();
for(int i=0;i<Available;i++)
{
int phase=(rand()%NumberofPhase);
biphase.SetPhase(Index+i,phase);
}
/*
for(int i=0;i<Available/2;i++)
{
int phase=2*(rand()%NumberofPhase/2);
biphase.SetPhase(Index+i*2,(phase+lastphase)/2);
biphase.SetPhase(Index+i*2+1,phase);
lastphase=phase;
}*/
/*for(int i=0;i<Available;i++)
{
lastphase=(lastphase+1)%NumberofPhase;
biphase.SetPhase(Index+i,lastphase);
}*/
for(int i=0;i<BURST_SIZE;i++)
{
int phase=(rand()%NumberofPhase);
PhaseBuffer[i]=phase;
}
biphase.SetPhaseSamples(PhaseBuffer,BURST_SIZE);
}
biphase.stop();
}
@ -408,9 +393,9 @@ int main(int argc, char* argv[])
}
//SimpleTest(Freq);
//SimpleTestbpsk(Freq);
SimpleTestbpsk(Freq);
//SimpleTestFileIQ(Freq);
SimpleTestDMA(Freq);
//SimpleTestDMA(Freq);
//SimpleTestAm(Freq);
//SimpleTestOOK(Freq);
//SimpleTestBurstFsk(Freq);

2
src/fskburst.cpp
View file

@ -73,7 +73,7 @@ This program is free software: you can redistribute it and/or modify
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
cbp->dst = 0x7E000000 + (PLLA_FRAC<<2) + CLK_BASE ;
cbp->dst = 0x7E000000 + (PLLC_FRAC<<2) + CLK_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);

48
src/gpio.cpp
View file

@ -87,6 +87,7 @@ int clkgpio::SetPllNumber(int PllNo, int MashType)
else
Mash = 0;
gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber /*|(1 << 5)*/; //5 is Reset CLK
usleep(100);
gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber /*|(1 << 5)*/; //5 is Reset CLK
usleep(100);
Pllfrequency = GetPllFrequency(pllnumber);
@ -124,6 +125,7 @@ int clkgpio::SetClkDivFrac(uint32_t Div, uint32_t Frac)
{
gpioreg[GPCLK_DIV] = 0x5A000000 | ((Div) << 12) | Frac;
usleep(100);
gpioreg[GPCLK_DIV_2] = 0x5A000000 | ((Div) << 12) | Frac;
usleep(100);
fprintf(stderr, "Clk Number %d div %d frac %d\n", pllnumber, Div, Frac);
@ -136,9 +138,9 @@ int clkgpio::SetMasterMultFrac(uint32_t Mult, uint32_t Frac)
{
//fprintf(stderr,"Master Mult %d Frac %d\n",Mult,Frac);
gpioreg[PLLA_CTRL] = (0x5a << 24) | (0x21 << 12) | Mult; //PDIV=1
gpioreg[PLLC_CTRL] = (0x5a << 24) | (0x21 << 12) | Mult; //PDIV=1
usleep(100);
gpioreg[PLLA_FRAC] = 0x5A000000 | Frac;
gpioreg[PLLC_FRAC] = 0x5A000000 | Frac;
return 0;
}
@ -300,18 +302,20 @@ int clkgpio::SetCenterFrequency(uint64_t Frequency, int Bandwidth)
SetFrequency(0);
usleep(1000);
if ((gpioreg[CM_LOCK] & CM_LOCK_FLOCKA) > 0)
fprintf(stderr, "Master PLLA Locked\n");
if ((gpioreg[CM_LOCK] & CM_LOCK_FLOCKC) > 0)
fprintf(stderr, "Master PLLC Locked\n");
else
fprintf(stderr, "Warning ! Master PLLA NOT Locked !!!!\n");
fprintf(stderr, "Warning ! Master PLLC NOT Locked !!!!\n");
SetClkDivFrac(PllFixDivider, 0x0); // NO MASH !!!!
usleep(100);
usleep(100);
gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
usleep(100);
gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
usleep(100);
gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
usleep(100);
gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
usleep(100);
}
@ -338,26 +342,44 @@ void clkgpio::SetAdvancedPllMode(bool Advanced)
ModulateFromMasterPLL = Advanced;
if (ModulateFromMasterPLL)
{
SetPllNumber(clk_plla, 0); // Use PPL_A , Do not USE MASH which generates spurious
gpioreg[CM_PLLA] = 0x5A00022A; // Enable Plla_PER
//We must change Clk dependant from PLLC as we will modulate it
// switch the core over to PLLA
gpioreg[CORECLK_DIV] = (0x5a<<24) | (4<<12) ; // core div 4
usleep(100);
gpioreg[CORECLK_CNTL] = (0x5a<<24) | (1<<4) | (4); // run, src=PLLA
// switch the EMMC over to PLLD
int clktmp;
clktmp = gpioreg[EMMCCLK_CNTL];
gpioreg[EMMCCLK_CNTL] = (0xF0F&clktmp) | (0x5a<<24) ; // clear run
usleep(100);
gpioreg[EMMCCLK_CNTL] = (0xF00&clktmp) | (0x5a<<24) | (6); // src=PLLD
usleep(100);
gpioreg[EMMCCLK_CNTL] = (0xF00&clktmp) | (0x5a<<24) | (1<<4) | (6); // run , src=PLLD
SetPllNumber(clk_pllc, 0); // Use PLL_C , Do not USE MASH which generates spurious
//gpioreg[CM_PLLA] = 0x5A00022A; // Enable PllA_PER
gpioreg[CM_PLLC] = 0x5A00022A; // Enable PllA_PER
usleep(100);
uint32_t ana[4];
for (int i = 3; i >= 0; i--)
{
ana[i] = gpioreg[(A2W_PLLA_ANA0 ) + i];
ana[i] = gpioreg[(A2W_PLLC_ANA0 ) + i];
}
ana[1]&=~(1<<14); // No use prediv means Frequency
//ana[1] |= (1 << 14); // use prediv means Frequency*2
for (int i = 3; i >= 0; i--)
{
gpioreg[(A2W_PLLA_ANA0 ) + i] = (0x5A << 24) | ana[i];
gpioreg[(A2W_PLLC_ANA0 ) + i] = (0x5A << 24) | ana[i];
}
usleep(100);
gpioreg[PLLA_CORE] = 0x5A000000|(1<<8);//Disable
gpioreg[PLLA_PER] = 0x5A000001; // Divisor
gpioreg[PLLC_CORE0] = 0x5A000000|(1<<8);//Disable
gpioreg[PLLC_PER] = 0x5A000001; // Divisor
usleep(100);
}
}
@ -367,14 +389,14 @@ void clkgpio::SetPLLMasterLoop(int Ki,int Kp,int Ka)
uint32_t ana[4];
for (int i = 3; i >= 0; i--)
{
ana[i] = gpioreg[(A2W_PLLA_ANA0 ) + i];
ana[i] = gpioreg[(A2W_PLLC_ANA0 ) + i];
}
ana[1]=(Ki<<A2W_PLL_KI_SHIFT)|(Kp<<A2W_PLL_KP_SHIFT)|(Ka<<A2W_PLL_KA_SHIFT);
fprintf(stderr,"Loop parameter =%x\n",ana[1]);
for (int i = 3; i >= 0; i--)
{
gpioreg[(A2W_PLLA_ANA0 ) + i] = (0x5A << 24) | ana[i];
gpioreg[(A2W_PLLC_ANA0 ) + i] = (0x5A << 24) | ana[i];
}
usleep(100) ;
//Only PLLA for now

74
src/gpio.h
View file

@ -97,6 +97,79 @@ class generalgpio:public gpio
#define EMMCCLK_CNTL (0x1C0/4)
#define EMMCCLK_DIV (0x1C4/4)
#define CM_VPUCTL 0x008
#define CM_VPUDIV 0x00c
#define CM_SYSCTL 0x010
#define CM_SYSDIV 0x014
#define CM_PERIACTL 0x018
#define CM_PERIADIV 0x01c
#define CM_PERIICTL 0x020
#define CM_PERIIDIV 0x024
#define CM_H264CTL 0x028
#define CM_H264DIV 0x02c
#define CM_ISPCTL 0x030
#define CM_ISPDIV 0x034
#define CM_V3DCTL 0x038
#define CM_V3DDIV 0x03c
#define CM_CAM0CTL 0x040
#define CM_CAM0DIV 0x044
#define CM_CAM1CTL 0x048
#define CM_CAM1DIV 0x04c
#define CM_CCP2CTL 0x050
#define CM_CCP2DIV 0x054
#define CM_DSI0ECTL 0x058
#define CM_DSI0EDIV 0x05c
#define CM_DSI0PCTL 0x060
#define CM_DSI0PDIV 0x064
#define CM_DPICTL 0x068
#define CM_DPIDIV 0x06c
#define CM_GP0CTL 0x070
#define CM_GP0DIV 0x074
#define CM_GP1CTL 0x078
#define CM_GP1DIV 0x07c
#define CM_GP2CTL 0x080
#define CM_GP2DIV 0x084
#define CM_HSMCTL 0x088
#define CM_HSMDIV 0x08c
#define CM_OTPCTL 0x090
#define CM_OTPDIV 0x094
#define CM_PCMCTL 0x098
#define CM_PCMDIV 0x09c
#define CM_PWMCTL 0x0a0
#define CM_PWMDIV 0x0a4
#define CM_SLIMCTL 0x0a8
#define CM_SLIMDIV 0x0ac
#define CM_SMICTL 0x0b0
#define CM_SMIDIV 0x0b4
/* no definition for 0x0b8 and 0x0bc */
#define CM_TCNTCTL 0x0c0
# define CM_TCNT_SRC1_SHIFT 12
#define CM_TCNTCNT 0x0c4
#define CM_TECCTL 0x0c8
#define CM_TECDIV 0x0cc
#define CM_TD0CTL 0x0d0
#define CM_TD0DIV 0x0d4
#define CM_TD1CTL 0x0d8
#define CM_TD1DIV 0x0dc
#define CM_TSENSCTL 0x0e0
#define CM_TSENSDIV 0x0e4
#define CM_TIMERCTL 0x0e8
#define CM_TIMERDIV 0x0ec
#define CM_UARTCTL 0x0f0
#define CM_UARTDIV 0x0f4
#define CM_VECCTL 0x0f8
#define CM_VECDIV 0x0fc
#define CM_PULSECTL 0x190
#define CM_PULSEDIV 0x194
#define CM_SDCCTL 0x1a8
#define CM_SDCDIV 0x1ac
#define CM_ARMCTL 0x1b0
#define CM_AVEOCTL 0x1b8
#define CM_AVEODIV 0x1bc
#define CM_EMMCCTL 0x1c0
#define CM_EMMCDIV 0x1c4
#define CM_LOCK (0x114/4)
# define CM_LOCK_FLOCKH (1<<12)
# define CM_LOCK_FLOCKD (1<<11)
@ -170,6 +243,7 @@ class generalgpio:public gpio
#define XOSC_CTRL (0x1190/4)
#define XOSC_FREQUENCY 19200000
//Parent PLL
enum {clk_gnd,clk_osc,clk_debug0,clk_debug1,clk_plla,clk_pllc,clk_plld,clk_hdmi};
class clkgpio:public gpio

2
src/iqdmasync.cpp
View file

@ -96,7 +96,7 @@ void iqdmasync::SetDmaAlgo()
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
cbp->dst = 0x7E000000 + (PLLA_FRAC<<2) + CLK_BASE ;
cbp->dst = 0x7E000000 + (PLLC_FRAC<<2) + CLK_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);

2
src/ngfmdmasync.cpp
View file

@ -77,7 +77,7 @@ void ngfmdmasync::SetDmaAlgo()
cbp->info = BCM2708_DMA_NO_WIDE_BURSTS | BCM2708_DMA_WAIT_RESP ;
cbp->src = mem_virt_to_phys(&usermem[samplecnt*registerbysample]);
cbp->dst = 0x7E000000 + (PLLA_FRAC<<2) + CLK_BASE ;
cbp->dst = 0x7E000000 + (PLLC_FRAC<<2) + CLK_BASE ;
cbp->length = 4;
cbp->stride = 0;
cbp->next = mem_virt_to_phys(cbp + 1);

2
src/phasedmasync.cpp
View file

@ -28,7 +28,7 @@ phasedmasync::phasedmasync(uint64_t TuneFrequency,uint32_t SampleRateIn,int Numb
{
SampleRate=SampleRateIn;
SetMode(pwm1pinrepeat);
pwmgpio::SetPllNumber(clk_plla,0);
pwmgpio::SetPllNumber(clk_pllc,0);
tunefreq=TuneFrequency*NumberOfPhase;
#define MAX_PWM_RATE 360000000