Fix PLL rate for non PI4
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parent
d318058a17
commit
d139ff56fb
2 changed files with 8 additions and 2 deletions
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@ -36,15 +36,20 @@ dma::dma(int Channel,uint32_t CBSize,uint32_t UserMemSize) // Fixme! Need to che
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//Channel DMA is now hardcoded according to Raspi Model (DMA 7 for Pi4, DMA 14 for others)
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uint32_t BCM2708_PERI_BASE =bcm_host_get_peripheral_address();
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channel=Channel;
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if(BCM2708_PERI_BASE==0xFE000000)
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{
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channel= 7; // Pi4
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dbg_printf(1,"dma PI4 using channel %d\n",channel);
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}
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else
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{
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channel = 14; // Other Pi
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dbg_printf(1,"dma (NOT a PI4) using channel %d\n",channel);
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}
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dbg_printf(1,"Channel %d CBSize %u UsermemSize %u\n",Channel,CBSize,UserMemSize);
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dbg_printf(1,"channel %d CBSize %u UsermemSize %u\n",channel,CBSize,UserMemSize);
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mbox.handle = mbox_open();
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if (mbox.handle < 0)
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@ -177,7 +177,8 @@ uint64_t clkgpio::GetPllFrequency(int PllNo)
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Freq =( XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLH_CTRL] & 0x3ff) + XOSC_FREQUENCY * (uint64_t)gpioreg[PLLH_FRAC] / (1 << 20))/(2*(gpioreg[PLLH_CTRL] >> 12)&0x7) ;
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break;
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}
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//if(pi_is_2711) Freq*=2LL;
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if(!pi_is_2711) // FixMe : Surely a register which say it is a 2x
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Freq*=2LL;
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Freq=Freq*(1.0-clk_ppm*1e-6);
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dbg_printf(1, "Pi4=%d Xosc = %llu Freq PLL no %d= %llu\n",pi_is_2711,XOSC_FREQUENCY,PllNo, Freq);
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