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59 lines
1.8 KiB
Diff
59 lines
1.8 KiB
Diff
From 1a9d394ffb964839f90b4d4efd1b9730c16efd22 Mon Sep 17 00:00:00 2001
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From: William Wu <william.wu@rock-chips.com>
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Date: Mon, 4 Dec 2017 10:40:39 +0100
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Subject: [PATCH 3/5] arm64: dts: rockchip: add usb3 controller node for RK3328
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SoCs
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RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
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core's general architecture. It can act as static xHCI host
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controller, static device controller, USB 3.0/2.0 OTG basing
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on ID of USB3.0 PHY.
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Signed-off-by: William Wu <william.wu@rock-chips.com>
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
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1 file changed, 27 insertions(+)
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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index dabef1a21649..56e4a0649ec2 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
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@@ -917,6 +917,33 @@
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status = "disabled";
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};
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+ usbdrd3: usb@ff600000 {
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+ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
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+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
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+ <&cru ACLK_USB3OTG>;
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+ clock-names = "ref_clk", "suspend_clk",
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+ "bus_clk";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ usbdrd_dwc3: dwc3@ff600000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x0 0xff600000 0x0 0x100000>;
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+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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+ dr_mode = "otg";
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+ phy_type = "utmi_wide";
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis_u2_susphy_quirk;
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+ snps,dis_u3_susphy_quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ status = "disabled";
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+ };
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+ };
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+
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gic: interrupt-controller@ff811000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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--
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2.21.0
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