Fix issues with PDIV and PLL setup
This commit is contained in:
F5OEO
parent
1dac6e6948
commit
b82638a3ca
101
src/gpio.cpp
101
src/gpio.cpp
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@ -66,7 +66,9 @@ dmagpio::dmagpio() : gpio(GetPeripheralBase() + DMA_BASE, DMA_LEN)
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// ***************** CLK Registers *****************************************
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clkgpio::clkgpio() : gpio(GetPeripheralBase() + CLK_BASE, CLK_LEN)
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{
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SetppmFromNTP();
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//SetppmFromNTP();
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padgpio level;
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level.setlevel(7); //MAX Power
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}
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clkgpio::~clkgpio()
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@ -118,7 +120,7 @@ uint64_t clkgpio::GetPllFrequency(int PllNo)
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Freq = XOSC_FREQUENCY * ((uint64_t)gpioreg[PLLH_CTRL] & 0x3ff) + XOSC_FREQUENCY * (uint64_t)gpioreg[PLLH_FRAC] / (1 << 20);
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break;
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}
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fprintf(stderr, "Freq = %llu\n", Freq);
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//fprintf(stderr, "Freq = %llu\n", Freq);
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return Freq;
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}
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@ -128,11 +130,9 @@ int clkgpio::SetClkDivFrac(uint32_t Div, uint32_t Frac)
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gpioreg[GPCLK_DIV] = 0x5A000000 | ((Div) << 12) | Frac;
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usleep(100);
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//gpioreg[GPCLK_DIV_2] = 0x5A000000 | ((Div) << 12) | Frac;
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//usleep(100);
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fprintf(stderr, "Clk Number %d div %d frac %d\n", pllnumber, Div, Frac);
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//gpioreg[GPCLK_CNTL]= 0x5A000000 | (Mash << 9) | pllnumber |(1<<4) ; //4 is START CLK
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// usleep(10);
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//fprintf(stderr, "Clk Number %d div %d frac %d\n", pllnumber, Div, Frac);
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return 0;
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}
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@ -151,14 +151,17 @@ int clkgpio::SetFrequency(double Frequency)
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{
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if (ModulateFromMasterPLL)
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{
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double FloatMult = ((double)(CentralFrequency + Frequency) * PllFixDivider) / ((double)(XOSC_FREQUENCY) * (1 - clk_ppm * 1e-6)); // -ppm : compensate ppm
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double FloatMult=0;
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if(PllFixDivider==1) //Using PDIV thus frequency/2
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FloatMult = ((double)(CentralFrequency + Frequency) ) / ((double)(XOSC_FREQUENCY*2) * (1 - clk_ppm * 1e-6));
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else
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FloatMult = ((double)(CentralFrequency + Frequency)*PllFixDivider ) / ((double)(XOSC_FREQUENCY) * (1 - clk_ppm * 1e-6));
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uint32_t freqctl = FloatMult * ((double)(1 << 20));
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int IntMultiply = freqctl >> 20; // Need to be calculated to have a center frequency
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freqctl &= 0xFFFFF; // Fractionnal is 20bits
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uint32_t FracMultiply = freqctl & 0xFFFFF;
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//uint32_t FracMultiply = 0.75*(1<<20);
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SetMasterMultFrac(IntMultiply, FracMultiply);
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}
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else
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@ -180,7 +183,11 @@ uint32_t clkgpio::GetMasterFrac(double Frequency)
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{
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if (ModulateFromMasterPLL)
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{
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double FloatMult = ((double)(CentralFrequency + Frequency) * PllFixDivider) / ((double)(XOSC_FREQUENCY) * (1 - clk_ppm * 1e-6));
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double FloatMult=0;
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if(PllFixDivider==1) //Using PDIV thus frequency/2
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FloatMult = ((double)(CentralFrequency + Frequency) ) / ((double)(XOSC_FREQUENCY*2) * (1 - clk_ppm * 1e-6));
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else
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FloatMult = ((double)(CentralFrequency + Frequency)*PllFixDivider ) / ((double)(XOSC_FREQUENCY) * (1 - clk_ppm * 1e-6));
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uint32_t freqctl = FloatMult * ((double)(1 << 20));
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int IntMultiply = freqctl >> 20; // Need to be calculated to have a center frequency
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freqctl &= 0xFFFFF; // Fractionnal is 20bits
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@ -200,7 +207,7 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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// Constants taken https://github.com/raspberrypi/linux/blob/ffd7bf4085b09447e5db96edd74e524f118ca3fe/drivers/clk/bcm/clk-bcm2835.c#L1763
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#define MIN_PLL_RATE 400e6
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#define MIN_PLL_RATE_USE_PDIV 1700e6
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#define MAX_PLL_RATE 3e9
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#define MAX_PLL_RATE 4e9
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#define XTAL_RATE 19.2e6
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double xtal_freq_recip = 1.0 / XTAL_RATE; // todo PPM correction
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int best_divider = 0;
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@ -208,7 +215,7 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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int solution_count = 0;
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//printf("carrier:%3.2f ",carrier_freq/1e6);
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int divider=0, min_int_multiplier, max_int_multiplier, fom, int_multiplier, best_fom = 0;
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double Multiplier=0.0;
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best_divider = 0;
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bool cross_boundary=false;
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if(Frequency<MIN_PLL_RATE/4095)
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@ -221,8 +228,10 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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fprintf(stderr, "Frequency too high !!!!!!\n");
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return -1;
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}
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if(Frequency*2>MIN_PLL_RATE_USE_PDIV)
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if(Frequency*2>MIN_PLL_RATE_USE_PDIV)
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{
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best_divider=1; // We will use PREDIV 2 for PLL
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}
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else
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{
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for (divider = 4095; divider > 1; divider--)//1 is allowed only for MASH=0
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@ -256,7 +265,7 @@ int clkgpio::ComputeBestLO(uint64_t Frequency, int Bandwidth)
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{
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PllFixDivider = best_divider;
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if(cross_boundary) fprintf(stderr,"Warning : cross boundary frequency\n");
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fprintf(stderr, "Found solution : divider:%d VCO: %4.1fMHz\n", best_divider,Frequency * best_divider * xtal_freq_recip);
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fprintf(stderr, "Found PLL solution for frequency %4.1fMHz : divider:%d VCO: %4.1fMHz\n", (Frequency/1e6), PllFixDivider,(Frequency/1e6) *((PllFixDivider==1)?2.0:(double)PllFixDivider));
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return 0;
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}
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else
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@ -301,14 +310,8 @@ int clkgpio::SetCenterFrequency(uint64_t Frequency, int Bandwidth)
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//Choose best PLLDiv and Div
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ComputeBestLO(Frequency, Bandwidth); //FixeDivider update
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SetFrequency(0);
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usleep(1000);
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if ((gpioreg[CM_LOCK] & CM_LOCK_FLOCKC) > 0)
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fprintf(stderr, "Master PLLC Locked\n");
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else
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fprintf(stderr, "Warning ! Master PLLC NOT Locked !!!!\n");
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if(PllFixDivider==1)
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{
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//We will use PDIV by 2, means like we have a 2 times more
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@ -327,6 +330,9 @@ int clkgpio::SetCenterFrequency(uint64_t Frequency, int Bandwidth)
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for (int i = 3; i >= 0; i--)
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{
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ana[i] = gpioreg[(A2W_PLLC_ANA0 ) + i];
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usleep(100);
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//fprintf(stderr,"PLLC %d =%x\n",i,ana[i]);
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ana[i] &= ~(1<<14);
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}
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if(PllFixDivider==1)
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@ -336,30 +342,50 @@ int clkgpio::SetCenterFrequency(uint64_t Frequency, int Bandwidth)
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}
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else
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{
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ana[1]&=~(1<<14); // No use prediv means Frequency
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ana[1]|=(0<<14); // No use prediv means Frequency
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}
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/*
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* ANA register setup is done as a series of writes to
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* ANA3-ANA0, in that order. This lets us write all 4
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* registers as a single cycle of the serdes interface (taking
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* 100 xosc clocks), whereas if we were to update ana0, 1, and
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* 3 individually through their partial-write registers, each
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* would be their own serdes cycle.
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*/
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for (int i = 3; i >= 0; i--)
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{
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gpioreg[(A2W_PLLC_ANA0 ) + i] = (0x5A << 24) | ana[i];
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ana[i]|=(0x5A << 24) ;
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gpioreg[(A2W_PLLC_ANA0 ) + i] = ana[i];
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//fprintf(stderr,"Write %d = %x\n",i,ana[i]);
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usleep(100);
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}
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/*
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for (int i = 3; i >= 0; i--)
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{
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fprintf(stderr,"PLLC after %d =%x\n",i,gpioreg[(A2W_PLLC_ANA0 ) + i]);
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}
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*/
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SetFrequency(0);
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usleep(100);
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if ((gpioreg[CM_LOCK] & CM_LOCK_FLOCKC) > 0)
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fprintf(stderr, "Master PLLC Locked\n");
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else
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fprintf(stderr, "Warning ! Master PLLC NOT Locked !!!!\n");
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usleep(100);
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gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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usleep(100);
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//gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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//usleep(100);
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gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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usleep(100);
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//gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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//usleep(100);
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}
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else
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{
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GetPllFrequency(pllnumber); // Be sure to get the master PLL frequency
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gpioreg[GPCLK_CNTL] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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//gpioreg[GPCLK_CNTL_2] = 0x5A000000 | (Mash << 9) | pllnumber | (1 << 4); //4 is START CLK
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}
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return 0;
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}
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@ -409,20 +435,23 @@ void clkgpio::SetAdvancedPllMode(bool Advanced)
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void clkgpio::SetPLLMasterLoop(int Ki,int Kp,int Ka)
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{
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uint32_t ana[4];
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uint32_t ana[4];
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for (int i = 3; i >= 0; i--)
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{
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ana[i] = gpioreg[(A2W_PLLC_ANA0 ) + i];
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}
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ana[1]=(Ki<<A2W_PLL_KI_SHIFT)|(Kp<<A2W_PLL_KP_SHIFT)|(Ka<<A2W_PLL_KA_SHIFT);
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//Fixe me : Should make a OR with old value
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ana[1]&=(uint32_t)~((0x7<<A2W_PLL_KI_SHIFT)|(0xF<<A2W_PLL_KP_SHIFT)|(0x7<<A2W_PLL_KA_SHIFT));
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ana[1]|=(Ki<<A2W_PLL_KI_SHIFT)|(Kp<<A2W_PLL_KP_SHIFT)|(Ka<<A2W_PLL_KA_SHIFT);
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fprintf(stderr,"Loop parameter =%x\n",ana[1]);
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for (int i = 3; i >= 0; i--)
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{
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gpioreg[(A2W_PLLC_ANA0 ) + i] = (0x5A << 24) | ana[i];
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usleep(100);
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}
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usleep(100) ;
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//Only PLLA for now
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}
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@ -864,6 +893,6 @@ padgpio::~padgpio()
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int padgpio::setlevel(int level)
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{
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gpioreg[PADS_GPIO_0]=0x5a000000 + (level&0x7) + (0<<4) + (0<<3);
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gpioreg[PADS_GPIO_0]=(0x5a<<24) | (level&0x7) | (0<<4) | (0<<3);
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return 0;
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}
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@ -87,7 +87,7 @@ class generalgpio:public gpio
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#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l))
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#define CLK_BASE (0x00101000)
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#define CLK_LEN 0x1300
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#define CLK_LEN 0x1660
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#define CORECLK_CNTL (0x08/4)
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#define CORECLK_DIV (0x0c/4)
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